beginner_EDA
Full Member level 4
Hi,
I am trying to run following reference design for 6G-SDI:
https://www.xilinx.com/support/docu...e-sdi-interfaces-7series-gtx-transceivers.pdf
As mentioned in its page 9, MGTREFCLK input is provided as follows:
But I didn't understand the location index(X0Y6, X0Y7) after IBUFDS_GTE2_. How it is determined? if I am using another transceiver having different MGTREFCLK, does this index also change or always reamains same?
Furthermore, it is written that QPLL is operating in range 1. How and where to set range 1 (in case of 6G) and range 2(incase of 12G, see page 10/11) in the code?
Actually the refernce design is written for 12G in xc7k325t-3 and I am modifying it for xc7k325t-2 with the help of wrapper file given for 6G.
I am trying to run following reference design for 6G-SDI:
https://www.xilinx.com/support/docu...e-sdi-interfaces-7series-gtx-transceivers.pdf
As mentioned in its page 9, MGTREFCLK input is provided as follows:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 // MGTREFCLK input buffers (* LOC = "IBUFDS_GTE2_X0Y6" *) IBUFDS_GTE2 MGTCLKIN0 ( .I (FMC_HPC_GBTCLK0_M2C_C_P), .IB (FMC_HPC_GBTCLK0_M2C_C_N), .CEB (1'b0), .O (mgtclk_148_5), .ODIV2 ()); (* LOC = "IBUFDS_GTE2_X0Y7" *) IBUFDS_GTE2 MGTCLKIN1 ( .I (FMC_HPC_GBTCLK1_M2C_C_P), .IB (FMC_HPC_GBTCLK1_M2C_C_N), .CEB (1'b0), .O (mgtclk_148_35), .ODIV2 (drpclk_in));
But I didn't understand the location index(X0Y6, X0Y7) after IBUFDS_GTE2_. How it is determined? if I am using another transceiver having different MGTREFCLK, does this index also change or always reamains same?
Furthermore, it is written that QPLL is operating in range 1. How and where to set range 1 (in case of 6G) and range 2(incase of 12G, see page 10/11) in the code?
Actually the refernce design is written for 12G in xc7k325t-3 and I am modifying it for xc7k325t-2 with the help of wrapper file given for 6G.
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