how to Convert synthesized VHDL/Verilog to spice netlist

[wildwood]

verilog to spice

Dear All,

I'm trying to get Spice netlist file from Verilog/VHDL. After I
synthesized the vhdl file using DesignCompiler, what tools available that
can help me to get the spice netlist. I need the interconnect
information incorporated in the spice netlist. Any help will be very
useful
Thanks in advance,

 

[leeguoxian]

nettran

I am not sure, I think u can get the spice netlist after P&R

 

[tlihu]

vhdl spice netlist

My colleague wrote programs in C language to convert Verilog codes into SPICE netlist. I'd like to know if there is any public tools available yet.

 

[jackson_peng]

spice cadence verilog

use "nettran" command, provided by hercules.

 

[bravobravo]

spice netlist format

hsim have this tools : v2h ....
Or use ECS from Cohesion ..

BRs

 

[pyth2004]

vhdl netlist to spice netlist

Hi,

you can import the synthesized verilog into Cadence and then export it as spice netlist in "analog" format.

 

[ls000rhb]

vhdl to netlist

v2lvs in calibre

 

[wkong_zhu]

v2lvs -a

yes, use v2lvs in Calibre.
v2lvs -l umc.spi -v verilog1.v -v verilog2.v -s hardblock.spi top_cts.v -o top_cts.spi

 

[wildwood]

pspice vhdl tools

use "nettran" command, provided by hercules.

thx very much .

thx every body .

I use nettran in hercules .

nettran -verilog file.v -verilog-b0 vss -verilog-b1 vdd -outType spice -outName file.spi

is it the right commond ?

I've got the spice netlist . but still there is some warnings .

thx all .

when i simulate in nanosim , is it necessary to add spice model ?

 

[asping]

vhdl to spice netlist converter

v2lvs in calibre
verilogIn in cadence
and similar tool in Herculs of synopsys but I cannot remember the name