65nm technology challenges

[rakesh1234]

Hi all,
I want to know what different kind of challenges occur at 65nm technology.
Please elaborate your answers .
I need it urgent.
Also Let me know the interview questions that may be asked for a physical design engg.

 

[au_sun]

Challenges in 65 nm,

- leakage power, SI issues are more prominent in 65nm.

SI can cause timing violations. Fixing SI triggered violation requires proper analysis.

for Leakage power reduction various techniques such as using multi Vth cells, Power down circuits, are adapted during the design flow.

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[shavakmm]

my blog may be helpful to you for your interview preparations:

https://vlsifaq.blogspot.com/search/label/Physical Design

rgds murali
https://asic-soc.blogspot.com

 

[rakesh1234]

still I want to know the various drc rule for nano technology

 

[research235]

drc rules .. check the calibre rules file .. u will know ..

 

[rakesh1234]

where should I find it ?

 

[research235]

if u have mentor calibre license .... go check for manuals . u wll find it in that

suresh

 

[rakesh1234]

I dont have it

 

[master_picengineer]

Take a look at this following nice book.

Hope it help.
Regards,
Master_picengineer.