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Cadence may introduce a 64-bit version of their ic5.0 software later (or at least some parts of it), though I do not know when. I have seen this info in a shortform flyer downloaded from their web-site a few weeks ago (if my memory is correct). This shortform flyer described Cadence's plans regarding what software to port to Linux and whether that would be in 32 or 64-bit versions.
But to have any use of a 64-bit software you will also have to run it on a 64-bit CPU. Not all Intel's faster CPUs are 64-bit. In fact I think that most of them are 32-bit, which makes it senseless to run 64-bit applications on them. Also, it may be so that Intel's 64-bit CPUs runs on slower (clock) speed than their fastest 32-bit CPUs, so the performance increase in using 64-bit software may to a large extent be lowered for this reason.
/Pim
mariaR said:
Can anyone give me a list of 64bits EDA application for cip design.
OK! you all know, Itanium, the new CPU from intel is a 64 bits cpu. It uses a completely new architecture than previous microprocessors. An EPIC ( Explicitly Parallel Instruction Computing , I think ) architecture is used to make a high performance MIMD engine.
However, why we should use 64 bits CPUs for our ( for example ) chip place and route process? I think high performance 32 bits CPU such as P4 or Athlon will be enough, those 64 bits CPUs are mainly produced for servers I think.
why we should use 64 bits CPUs for our ( for example ) chip place and route process? I think high performance 32 bits CPU such as P4 or Athlon will be enough, those 64 bits CPUs are mainly produced for servers I think.
The big difference between 32 bits and 64 bits application is the size of dababase it can handle: 32 bits limitation is 2-4GB, there is almost no limitation for 64bits application. The chipp become bigger and bigger, parasitites netlist grow in exponential. The old 32 bits can handle such big design anymore.
Just check in task manager (if you are running SW under windows) how much ram takes xilinx P/R tool during the mapping or routing stage of XC2V6000 and you will be terrified. Modelsim is also resource hungry during the simulation (especially timing) of large designs, and 2-4GB is not enough or will soon not be enough. I’m also modeling some complex structures and machines with CAD SW and I already bumped into 2GB limitation several times. I’m eagerly awaiting arrival of athlon64/Opteron.
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