starman2578
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I need to make a 6 bit full adder using verilog(Xilinx).And I need to use a 4 bit adder and two 1 bit adders. Can you guys please help me?
This is how I start:
module adder6(
output[6:0] sum,
input[5:0] a, b);
This is how I start:
module adder6(
output[6:0] sum,
input[5:0] a, b);