want to know how to convert verilog netlist to spice netlist

[likun0427]

verilog spice translator

spice netlist is required when using powermill(synopsys) to analyze power of the chip.
in Calibre, one command v2lvs is one way.
in panda, one command ver2cdl is another way to convert.

but, top module of the verilog netlist includes some IP which has no spice.

thanks for your suggestion!

 

[zhustudio]

verilog to spice

nettran in Hercules is another verilog to spice translator. You can merge the IP's CDL to the whole netlist. Or you can use nanosim to analyze the power.

 

[aaronhor]

you can use v2lvs command . More details can be found on the link:

How to convert Verilog code to Spice format | Circuit Design World

 

[tariq786]

if your code is RTL, you can use a PERL or PYTHON script to do the translation yourself. Its not that hard.