[50 pts][Urgent Req] gm/Id methodology for transistor sizing

[AdvaRes]

gm id methodology

Hi all,

I need progressive tutorials (if possible exercices and solutions) on the gm/Id methodology for circuit's transistor sizing.
I know the principle but I can't apply it when dealing with differenctial circuit like differential delay cells.

Any help will be welcommed.
Thanks in advance.

Cheers,
Advares.

 

[erikl]

gm/id methodology

... Any help will be welcommed.
Thanks in advance.

Cheers,
Advares.

Hi again, Advares,
the book isn't yet published, but here's a workshop from the author.
Cheers, erikl
__
PS: No points required!

 

[AdvaRes]

the gm/id methodology

Hi Erikl !
Thank you so much.
I heard about this book and I'm waiting for it.

Advares.

 

[ashish_chauhan]

gm id methodology+books

Hi Advares,

You can try using the PAD tool by Danica Stefnovic... from EPFL...

for basic analog structues like miller opamp, folded cascode current mirror etc it gives enough insight into gm/id method...

 

[AdvaRes]

gm id methodology

Hi Advares,

You can try using the PAD tool by Danica Stefnovic... from EPFL...

for basic analog structues like miller opamp, folded cascode current mirror etc it gives enough insight into gm/id method...

Thanks ashish_chauhan,
Could you please provide a link to the tool ?

 

[ashish_chauhan]

gm/id pad

**broken link removed**

hope you get something from it!!
good luck

 

[novaming]

thanks for erikl's workshop~~~