[50 pts]PLL Total Phase noise

[mouzid]

total phase noise

Hello edaboarders,

How to plot the total phase noise of a PLL after having plotted the phase noise of the VCO, PFD,CP, filter and divider with Spectre.

I know that I have to add these curves but I dont know how to do it using the caclulator. I used + function but the result is wrong !

Please help.

 

[Y.C Park]

Hi

U can plot VCO phase noise itself.
Now U want to plot of total PLL's performance.
Considering my before experience, it's so difficult to simulate
Because you used PSS and PNoise function of spectreRF.
If you have enough time and physical memory of your machine, You can do
exact same method as VCO phase noise.
My suggestion
1. How about use UltraSim. ( In fact I've never ever used before )
2. make a Behavioral model of each analog block of PLL
and simulate one by one. U can get the effect of each analog block to PLL.
If you get the good solution, Please share me.
Thanks

 

[oermens]

Refer to https://www.designers-guide.org/Analysis/

 

[mouzid]

Thanks for your replies guys.
Actually I need the practical approche using the icfb calculator.
I have to plot the amplitude curve which is the sum of all the differents component noise.

https://en.wikipedia.org/wiki/File:Bode_Pole-Zero_Magnitude_Plot.PNG

Please help It's urgent.

 

[Raviprasad_K]

Hi,

If you can run the complete PLL in closed loop mode, you can directly plot the phase noise of output clock. But it is difficult to run the simulation for the duration of lock.

If the simulation is done separately for different modules, below is what you can do:
It is random noise. Thus direct addition of noise of different blocks does not hold good. RMS addition should be done to get the proper result.
It can be done in three steps:

1) Convert db plots to normal plots
2) Do rms addition and get a resultant plot
3) Convert the resulting plot to dB again

Let me know if it solves the problem.

 

[mouzid]

Hi,

If you can run the complete PLL in closed loop mode, you can directly plot the phase noise of output clock. But it is difficult to run the simulation for the duration of lock.

If the simulation is done separately for different modules, below is what you can do:
It is random noise. Thus direct addition of noise of different blocks does not hold good. RMS addition should be done to get the proper result.
It can be done in three steps:

1) Convert db plots to normal plots
2) Do rms addition and get a resultant plot
3) Convert the resulting plot to dB again

Let me know if it solves the problem.

Thanks Raviprasad_K for your reply,
That's just what I wanna know and do.
Could you please tell me what do you mean by normal plots ?
How to convert these plots and do the sum of the differents plots using the Calculator ?

Thanks.

 

[Raviprasad_K]

Hi,

When I referred to 'normal plot' it is magnitude plot.

Plot the phase noise in magnitude instead of dB. This saves you one step!

Say w1 and w2 are the magnitude plots of two blocks.
Now effective noise w3= sqrt((w1*w1+w2*w2)/2)
Convert w3 to dB plot = 20log10(w3)
You have the effective phase noise plot in dB!

 

[erikl]

... Now effective noise w3= sqrt((w1*w1+w2*w2)/2)

Why would you divide by 2 ? Ex: if w1=3 , w2=4 then w3=3.536 < w2 !