[50 pts for real help]Design compiler limits

[AdvaRes]

Hi all,


I know that DC doesnt support asynchronous feedbacks.
Does it support multiclocking ? clock gating ?

Could you please enumerate what design compiler doesn't support also ?

 

[jaydip]

ofcourse, DC supports multi clocking and clock gating .. otherwise why industry is behind DC and DC license being so costly ?

 

[AdvaRes]

Thanks jaydip for your reply.
Actually, I'm looking for the reason making designers use full custom tools for the design of their components instead of DC. For exemple, asynchronous design is not suported by DC that generates loops during synthesis. What are the other things that DC can't support or can support but request a lot of effort ?

 

[cop02ia]

Uh, I think the concept used here is incorrect. People do full custom not because of multiple clocks & clock gating. You can go to the analog forum & ask why people do use full custom. They might give a better answer.

Maybe you can give some examples of designs which people do full custom instead of using digital libraries to clarify?

I think the main reason could be if they are doing an AoT (heavily analog-based design), they will create their own digital cells as they will have more control on dimensions (that's what I had to do). But this has nothing to do with DC specifically (or any other synthesis tool for that matter). It's just to avoid the whole digital flow altogether.

Else, you can always go mixed-signal (which I believe DC will be able to handle the digital part).
BTW, I'm not using DC at the moment, we only have RC licences here.

Best regards.

 

[jaydip]

asynchronous loops are what i know is not supported easily by DC ... it needs so many constraints to get that kind of design through DC .. lets say, as such latch based designs are supported by DC but it requires more constraints than flop based design ..

may be other custom ASIC designers can throw more lights on it ...

 

[AdvaRes]

Hi guys !
Concerning clock gating I wanna implement my own technique. An Enable signal ANDed with the clock.

Some of you may understand multiclock circuits as dual edge triggered dff based design. That's not what I mean.
By multiclocking I mean multi clock domains. consider the exemple of a component operating at 100Mhz and a second one operating at 200MHz.

I have another question about multiplexing for DDR. When the clock is tied to the sel input of the Mux an error occur. Solution consist of setting false paths. How effecient is the solution ? Doesn't this result in bugs after real implementation of the circuit due to the false path setting ?

 

[shelby]

Full custom designs can achieve faster frequencies than standard cell approach. Full custom designs can make use of logic techniques such as domino logic that cannot be implemented using std cells.

Clock gating using (En&Clk) is the most basic clock gating approach but is sensitive to glitchs. This is why the latch based clock gating cells are commonly used.

What was the error you got for the DDR clk issue? I have seen designs do this without having a false path. Maybe there is a variable that needs to be set to allow clocks signals to be timed as datapaths when hitting a d pin?

 

[vlsichipdesigner]

hi,

my 2cents,

DC is a very matured tool, there for decades , seen tons of proven success of plenty of tapeouts to its data points .

few technical inputs
*Tool can break combinational loops and go ahead, it will saying in the warning that loop is there.
*multi mode scenarios can be performed.
* if muxes select lines is not constrained then it will optimize both the paths, so ideally constraining select lines is not a choice. if we want to remove unwanted paths, and means to reduce runtime then we can do so.
* tools are capable of plenty of logic optimization, register re-timing/constant propagation/register merging.
* clock-gating as mentioned earlier is a design strategy to have a single clock-gating cell based on latch based, to avoid glitches, and tools are strong enough , to optimize multiple clock-gating cells.
* Address power issues with UPF(unified power format).
* Tons of scan related optimizations.
* DC-Topo, to address the years old correlation issue of wire-load models.

and a strong handshake with synopsys tools like ICC , power compiler, DFT compiler, design wares,.... address logical/physical constraints to address area/power/timing/co-relation across tools/flows/yield/Test/...

How many tools come cannot come close to full-custom optimization, our Job security is at stake. this prooves humans are one step ahead with machines.

only question is time factor, automation, runtime, parallelism, hierarchical, human capital, we look for alternative which is tools and we need to live in practical world, with multiple projects and way to handle it.

Unfortunately tools are still a long way to go for analog designs.

myprayers,
chip design made easy
https://www.vlsichipdesign.com