subhrojyotisarkar
Newbie level 4
Hi,
Are arrays in verilog synthesizable? If yes, then how? Currently I made a long one dimensional vector of regs with a total length of 32768. And the addressing is a bit complex. Also, the RTL Compiler crashes while elaborating my design. It is not showing any error and starts elaborating. But after starting to map the ports, it suddenly shows an message "Insufficient memory. Total memory usage 233140kb. Exiting abnormally." and the program exits. How to get out of it?
Please help me out.
Are arrays in verilog synthesizable? If yes, then how? Currently I made a long one dimensional vector of regs with a total length of 32768. And the addressing is a bit complex. Also, the RTL Compiler crashes while elaborating my design. It is not showing any error and starts elaborating. But after starting to map the ports, it suddenly shows an message "Insufficient memory. Total memory usage 233140kb. Exiting abnormally." and the program exits. How to get out of it?
Please help me out.