|IAngel|
Member level 3
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simulation output resistance
Ok - so I posted a short time ago about my amp having a supply of 500mV, - supply of 0V, an open loop gain of about 60dB, a phase margin of 45°, and a CMR from 40mV to 450mV (roughly, here) that was found by making the amp a UG buffer and watching where the output followed the input.
However, when put in CL mode as an inverting amplifier, it fails. It was suggested to test my output impedance.
Here's where I need help: I tested the output impedance by leaving the Vdd, Vss, +ve and -ve inputs floating. I applied a test voltage of 1V at the output and measured the current going in. Dividing the test voltage by the current the simulator gave me, I got a resistance of about 125x10^12 Ohms (125 TOhms)... That's insane! Is that why my circuit is failing as a closed loop device? It seems to me that this would limit the amount of input to the output, and therefore allow the diff. pair to take care of the feedback - which would make me think that would work... What do you all think?
edit: I've now also tried grounding the Vdd, Vss, +ve and -ve inputs. applied a test voltage of 1V at the output and measured the current going in. Dividing the test voltage by the current the simulator gave me, I got a resistance of about 1.2k Ohms (1.2^10^3 Ohms). This seems quite low.
Which of the simulations should I trust for output impedance? Do I ground all the terminals of the circuit to test it, or do I leave them all floating to test it? Is there a better way to test output Impedance of a circuit with Cadence?
Should I try to lower the output impedance? And if so/not could you explain why and give suggestions?
Thanks! I appreciate the help!
Ok - so I posted a short time ago about my amp having a supply of 500mV, - supply of 0V, an open loop gain of about 60dB, a phase margin of 45°, and a CMR from 40mV to 450mV (roughly, here) that was found by making the amp a UG buffer and watching where the output followed the input.
However, when put in CL mode as an inverting amplifier, it fails. It was suggested to test my output impedance.
Here's where I need help: I tested the output impedance by leaving the Vdd, Vss, +ve and -ve inputs floating. I applied a test voltage of 1V at the output and measured the current going in. Dividing the test voltage by the current the simulator gave me, I got a resistance of about 125x10^12 Ohms (125 TOhms)... That's insane! Is that why my circuit is failing as a closed loop device? It seems to me that this would limit the amount of input to the output, and therefore allow the diff. pair to take care of the feedback - which would make me think that would work... What do you all think?
edit: I've now also tried grounding the Vdd, Vss, +ve and -ve inputs. applied a test voltage of 1V at the output and measured the current going in. Dividing the test voltage by the current the simulator gave me, I got a resistance of about 1.2k Ohms (1.2^10^3 Ohms). This seems quite low.
Which of the simulations should I trust for output impedance? Do I ground all the terminals of the circuit to test it, or do I leave them all floating to test it? Is there a better way to test output Impedance of a circuit with Cadence?
Should I try to lower the output impedance? And if so/not could you explain why and give suggestions?
Thanks! I appreciate the help!