a question on the hysteresis comparator design

[John Xu]

hi,
I am designing a hysteresis comparator with 0.6um CMOS. The circuit is the classic topology which I refered from the book "CMOS analog circuit design"by Philip E.Allen and Douglas R.Holberg. The hysteresis of comparator is implemented by positive feedback in the input stage of a high-gain,open loop comparator. Pls. refer to the attached schematic.

In simulation, I found the hysteresis is sensitive to the mismatch of the input stage. e.g., if I set the differtial pair of input stage at 4% mismatch,the hysteresis will disapeared. It is a serious issue, beasue per my understanding, 4% mismatch is normal for CMOS process.

Can anyone give any idea to improve the mismatch issue on it?

Thanks in advance!

 

[sunking]

1. enhance the tail current
2. careful layout <1% mismatch

 

[John Xu]

Hi Sunking,
Thanks for the helpful proposal. Woiuld you pls. explain the method "2. careful layout <1% mismatch " more clearly?

It means if I can layout it carefully,e.g., use centroid technique, it can be reduced to <1%?

For 0.6um CMOS, in nnormally, if I do the mismatch analysis, at what mismatch ratio, e.g.,1%,10%,or 15% should I consider in simulation?

Thanks in advance

 

[sunking]

make the input stage large W and L, then centroid symmetrcal itechnique.
%1 is ok