[SOLVED] Reference plane in the substrate stack-up for CMOS technology

[anh56789]

Hi everyone,

I'm working with 65nm CMOS technology and using the EM simulator from ADS software. I have attached a part of the EM substrate stack-up, and I have some questions about the bottom cover.

1. I was told that the perfect conductor at the bottom is used as a reference pin for every port in the EM simulation, except for differential ports. In GaN or GaAs technology, there is a backside metal, which I assumed the bottom cover also represented. However, in CMOS technology, there isn’t any metal beneath the final layer, which is the silicon substrate. How might this affect the validity of the EM simulation results?
2. After simulating the CMOS circuit, I generated an SNP file for circuit simulation and noticed that there is a reference pin for the bottom cover. I’m curious about the purpose of this pin, especially considering that the CMOS chip is placed on the center ground pad of the package with adhesive, leading to a connection from the bottom cover to the ground with finite impedance. What should we do regarding this pin when packaging the chip? Furthermore, I found that when simulating the SNP file with the reference pin connected to ground versus floating, the results differ.

Any insights on these issues would be greatly appreciated. If I haven’t made myself clear, please feel free to ask any questions. Thank you so much!

 

[dick_freebird]

Backside attributes vary by process, post-processing a.nd package.

You didn't mention SOI which has its own gaggle of options.

"Bulk" (uniform doped) at maybe 1 - 5 ohm-cm seems roughly right to me but that's old school. Full wafer thickness or thinned, and what backside if ground (bare, plated, eutectic attach, silver-glass, maybe now organics with or without conductive filler? Anyway your ref plane IMO is the die attach but most of the height is worthless bulk resistor except for thermal, coupling, latchup aspects and maybe you focus on the core device and handwave or crudely analyze the "peripheral" parts of the structure.

Epi material grows similar rho film on heavy doped handle for better latchup protection and stiffer chip ground. Same final wafer thickness.

Consider neighbor / proximity / spreading effects as vertical extent dwarfs electrically active lateral device extents by about 100 - 1000X.

 

[volker@muehlhaus]

I always simulate with metal at the bottom of the stackup, to have some physical ground reference instead of that magic "ground at infinity" that Momentum can provide as a last resort. I have not seen any issues with that, when used as described below.

No difference in results is expected regarding SnP reference node *IF* all your schematic ports are effectively floating w.r.t. the substrate backside, i.e. there is no common mode current from the schematic port to the SnP reference node. This implies hat your schematic Term have their refence node at some EM model pin/port, and do *NOT* connect to schematic GND.

I think you might see difference if you allow schematic Terms to drive current to the substrate backside node, by sharing the same schematic GND. That would *NOT* be physical, that path doesn't exist.

 

[anh56789]

Hi @volker@muehlhaus,

all your schematic ports are effectively floating w.r.t. the substrate backside
schematic Term have their refence node at some EM model pin/port, and do *NOT* connect to schematic GND.

I will summarize my thoughts to make sure I understand your point. If I have an EM model for a transmission line, testbench 1, 2, and 3 are both correct because schematic ports are effectively floating. testbench 1 and 3 are equivalent because they have reference pins connected to GND. Testbench 2 has a floating reference pin but as you mentioned above, there will be no difference between the results of 3 testbenches (1,2,3).
However, testbench 4 will be different due to the ideal connection created by the GND symbol, and the results may not be valid, but what if only the transmission line is taped out and measured with GSG probes, Is that testbench (4) VALID for measurement case?

 

[volker@muehlhaus]

Is that testbench (4) VALID for measurement case?

What I don't like about testcase 4 is the artificial ideal connection from input ground to output ground. Current can bypass the chip ground path by flowing thru ideal ground connections, I think this will be invalid.

What you could do to prevent that is grouping pins 1,2,3 into one differential port (pin2 and 3 assigned port ground), and grouping pins 3,4,5 into one differential port (pin5 and 6 assigned port ground). This way, the current into the signal line MUST return locally through THESE reference nodes, and can't take any other path. In that setup, connecting to Term grounds to GND would be ok, because current will still flow throug the EM chip ground path.

 

[anh56789]

So can I say that the measurement result of a transmission line is not valid? Because I think the measurement set-up will be like testbench 4 as the below picture

The ground (G) of input probe and output probe must be connected to a reference node, I though so because when I look at a document of PNA-X N5247A, I see this schematic:

I haven't taped out any transmission line yet, so I don't have much knowledge. Could you enlighten me on this? did I misunderstand something? Thank you so much!

 

[volker@muehlhaus]

So can I say that the measurement result of a transmission line is not valid?

No, this two port measurement is valid, because it implements what I described in the second paragraph above.

Only the 6-port symbol that you show in ADS is misleading, because it seems to provide 6 port data which would enable additional modes.

Pins is something different that ports!!!! I have an appnote on this topic, but I am afraid that this might confuse you even more.

So I keep it simple and recommend to simulate your line as 2-port in Momentum, with the grounds assigned as port reference in Momentum. This way, the data is "safe" no matter if you add an extra GND in schematic.

 

[anh56789]

Actually, I did read all of your appnotes and they are very helpful. After I read your above appnote few months ago, I always use implicit ports in my EM set-up. However when applying for the measurement case, I think I made a mistake when connecting ports to the ideal GND. Thank you for enlightening me on that. I have a very last question about this one.
In case, I have a lot of blocks in my system (mixer + transmission line + amplifier), If I have to cut the layout and do EM for each block individually, with their input and output signals, should I use implicit or explicit ports (differential) in EM simulation? and If I use differential ports for input and output for each block, is there any possible problem when I combine them together on schematic to estimate the performance of the system? thank you so much!

 

[volker@muehlhaus]

For your S2P measurement there are no consequences regarding GND connection, because it's a 2-port, and there can't be any other current path, even if you wire it externally to the 6-port symbol and make mistakes with the grounds of that 6-port. Sorry for the confusion, maybe you create a little testcase like I did for the appnote, to verify all this yourself. It is a very important concept that I want you to understand well.

Regarding your EM blocks: in many cases it is safe to cascase blocks with differential ports. One exception that I can see is something like an inductor with ground frame that will have circular eddy currents running in circles in the ground frame, in this case you would "close the current loop" if you have two ground pins and connect them by making them both the negative terminal of a differential port.

The implicit port solution (all references at same potential, e.g. backside of substrate) has that possible issue of shorting some EM ground path by an ideal connection at schematic level, when placing multiple GND symbols at multiple ports. So you need to be very careful there, when placing GND symbol to EM data blocks or circuit elements. You can possibly use differential ports at those locations where an external device (transistor etc) is connected to an EM block, to make sure that THESE ports will not carry any current from the EM ground path to global schematic GND.

Sorry I have no better answer. In the end, it's all about possible current flow of ports with shared global ground vs. ports with explicit local ground.

 

[anh56789]

Thank you so much for your answer! It would help me a lot on my learning path. I want to ask one more question, we all know how to EM a single-ended transmission line but what about a differential one? Because in the differential transmission line, one line will act as a return current path for the other, do we have any pins for the adjacent ground?

 

[volker@muehlhaus]

but what about a differential one?

In an ideal world, it would be sufficient to model a differential port at the two wires, but in real world with curves and bends there will be some mode conversion to common mode. I have seen funny resonances in results if such common mode conversion happens, and the common mode is not terminated. So my modelling approach in that case are two ports on each end, with their reference pin(s)on the ground polygon(s), so that both differential model and common mode are supported.

At schematic level, when testing the line structure with no other devices, I use ADS balun4port elements. The two lines (wires) are connnected on one side, and the other side given you separate access to differential model and common mode.

 

[anh56789]

I have just set up an EM simulation for a differential transmission line, according to you which setup would be valid?

 

[volker@muehlhaus]

according to you which setup would be valid?

Setup 2

 

[anh56789]

thank you so much!