Adding parasitic Cap in pre-layout simulation

[Alice Lee]

Hi,everyone.
I want to know do u adding some parasitic Caps in ur schematic when running per-layout simu?
How to model these caps? I think they are mainly routing parasitic caps.....
BTW, the process is tsmc28nm HPC
thank u

 

[dick_freebird]

If you have a good guess at layout then do a plate or line capacitance calc. Then use pcapacitor elements for the loading (and do not neglect cross coupling or co-routed lines).

pcapacitors are neglected at LVS so won't bother that if you leave them in by neglect. If you use a variable in the cap value property like (12.3f*useCpar) then you can gang-enable or -disable this and that can help debug parasitics-affected results.

 

[Alice Lee]

If you have a good guess at layout then do a plate or line capacitance calc. Then use pcapacitor elements for the loading (and do not neglect cross coupling or co-routed lines).

pcapacitors are neglected at LVS so won't bother that if you leave them in by neglect. If you use a variable in the cap value property like (12.3f*useCpar) then you can gang-enable or -disable this and that can help debug parasitics-affected results.

thank u.