How to understand this Asynchronous SAR ADC

[wjxcom]

Hi all: look at this interesting sar topology, which still uses redundancy technology and uses Main-Sub-DAC Array. In this capacitor array, the highest and second highest bits are "taken" from 22 unit capacitors, but only 11 unit capacitors are used in the high position capacitor array, and the rest may be placed in the LSB capacitor array, but there are only 4 (or 3?) redundancy in the LSB array instead of 11. I don't understand, how do you put redundancy in the MSB array into the LSB array? This topology comes from Low-Power High-Performance SAR ADC with Redundancy and Digital Background Calibration，the author is Albert Hsu Ting Chang

Please help me, thax!!!

 

[D.A.(Tony)Stewart]

perhaps this will help

https://www.researchgate.net/publication/348227155_An_1839_fJConversion-Step_1-MSs_12-bit_SAR_ADC_with_Non-Binary_Multiple-LSB-Redundant_and_Non-Integer-and-Split-Capacitor_DAC