esd protection using a balun

[vlsi_design2]

It is believed that a transformer/balun at the input of the LNA provides ESD protection because primary and secondary are isolated. But a sudden esd discharge will propagate as a large AC signal through the balun and may damage the transistors. How does it protect in this situation?
Thanks

 

[KlausST]

Hi,

a balun is isolating, but is it designed for kilovolts of isolation?

Klaus

 

[D.A.(Tony)Stewart]

A BALUN converts unbalanced impedance for "signal and return" to balanced by raising the impedance common to both paths using high inductance while the differential inductance is nulled. This is also called a common-mode choke by raising the common-mode (CM) impedance. Adding shunt capacitance to each path after the choke to safety ground diverts the CM path from ESD.

 

[dick_freebird]

A thing to consider is that ESD (test) waveforms are in the 5-9ns
range, which is pretty low frequency by modern RF standards.
A balun primary meant for 5GHz might look pretty much like
a short (so eliminating a voltage breakdown concern, provided
that the ESD return path is Gnd as is the balun primary return)
at 100-200MHz. Presumably there would be some kind of bandpass
filter before the LNA (to keep out of band crud from saturating it,
if nothing else) and that might be the main protection. Or the first
victim, if an amp in 10ns will blow up your filter's caps. I'd bet there's
art about how to best arrange the low and high, and their components,
to get rugged at the antenna.

 

[BigBoss]

No matter element has been used at input, ESD protection scheme is always applied to sensitive circuits like LNA against worst case scenario.
An ESD protection circuit (simple didoes) will not effect the performance.

 

[D.A.(Tony)Stewart]

https://iopscience.iop.org/article/10.1088/1757-899X/600/1/012025/pdf detailed example

 

[biff44]

if you are using wire wound baluns, often there is a center tap involved with the balanced output terminals. that center tap is attached to the ground plane, and keeps big (low frequency, such as ESD events) input voltage spikes from leaking thru to the active devices

 

[vlsi_design2]

if you are using wire wound baluns, often there is a center tap involved with the balanced output terminals. that center tap is attached to the ground plane, and keeps big (low frequency, such as ESD events) input voltage spikes from leaking thru to the active devices

I am specifically asking about a balun where the single ended port is connected to IC pin and differential port is connected to say gate of NMOS transistors. Any ESD event in the single ended port can give rise to large differential swing at the gates as well which may damage the transistor. But I agree common mode spike will get grounded.

 

[D.A.(Tony)Stewart]

Possible mitigation strategies include:

1. ESD Protection: Implement additional ESD protection at the single-ended port to divert and absorb transient events, safeguarding the IC and connected transistors.
2. Filtering: Integrate filters to attenuate high-frequency components and suppress transient spikes, preventing them from reaching the sensitive NMOS gates.
3. Balanced Design: Explore alternative balun designs or differential signal paths that inherently mitigate the risk of large swings in the differential mode.

If there is a cable length between the devices and ESD is applied to the ground at one end the path that, then the ESD takes may be unknown as to which ground the ESD current takes. ESD events may be as low as 10 ps range ( as I have seen photographed) depending on the capacitance and ESR before the arc occurs. A very low ESR might occur when holding a metal object like a key or pen.

The discharge may create a ground wave which is common-mode.

A balun is quite suited to raise the CM impedance.

There are two types of ferrite balun windings;
- single windings on each side which create 10x more inductance and,
- bifilar windings which can achieve better CMRR or the ratio of DM/CM times the injected voltage.

TVS rail-clamps can function better with the raised current and bandwidth limiting from the Balun impedances from the risetime of L/R of the TVS resistance. and Balun inductance.

The TVS junction capacitance must be suitable for the data rate of the channel to minimize eye-pattern reduction at high speeds.