MPQ4470-AEC1 Layout guideline clarification

[newbie_hs]

Dear Team,

I am using MPQ4470-AEC1 in my design. In the datasheet page no 18 contains the layout guidelines.

I have some questions about guideline no:2 and no:3 .Those guidelines are given below.

1. Place input capacitors on both VIN sides (PIN8 and PIN19) and as close to the IN and GND pins as possible.
2. Place the decoupling capacitor as close to the VCC and GND pins as possible

Regarding placement ,they said only 'close' .
My question is how to calculate the maximum and minimum distance away from the IC so that I can place the parts(Capacitor).

Regards

 

[FvM]

The layout picture clarifies what "close" means. I'd translated it as minimal distance achievable with reasonable component spacing according to design rules.

 

[newbie_hs]

I completely agree with you.
But May I know how to calculate the distance theoretically

 

[FvM]

Minimal distance is monitored by your layout tool according to design rules in effect. Refer to assembly house requirements and IPC.

Maximal distance can't be simply calculated. You can estimate trace inductance by rules of thumb or determine it exactly in a FEM simulation. Know capacitor parasitic impedance and put all parameters in a SPICE simulation. Or just place capacitors "as close as possible" and verify switcher performance in real hardware.

 

[marce]

Close means next to... Place the critical components and related traces first...