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Electric voltage withstand capability of PCB layers.

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I am working on 11kW electric vehicle on-board charger.
With the PFC output voltage (DC link) = 800VDC (considering ripple, peak voltage = 840V), we have made layout such that +VE DC link & -VE DC link are overlapping on layers in multilayer (6 layer) PCB. It forms a PCB capacitor at such high voltages. So, is it recommended or is it fine with such layer structure.

How much voltage the two adjacent layer of FR4 PCB can withstand?
 

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Substrate thickness matters. For functional isolation (not safety related), I would use minimal 8 mil (0.2 mm) substrate. Preferably composed of 2 prepreg layers. CAF (conductive anodic filament growth) aware design might require thicker substrate.
 

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