[SOLVED] Input hysteresis at the IO-cells

[keyboardcowboy]

When the signal level rises above a certain high threshold, the system switches to a high state, and when the signal falls below a certain low threshold, the system switches to a low state. The key point is that the high and low thresholds are not the same – there's a region of uncertainty between them. This is the hysteresis.

Does SDHC/eMMC standard requires an input hysteresis at the IO-cells?.
I was looking at the SD Specifications Part 1 Physical Layer, and found this table

If input high is 1.6875v (0.625x2.7) and input low is -0.3v then does that mean the hysterisis is 1.6875- (-0.3)

 

[KlausST]

Hi,

There are two different input modes:
* true schmitt trigger behaviour with hysteresis ... what you describe above
* standard input: with "grey area" between HIGH and LOW. Signals in the grey area may (randomly) read as H or L. No hysteresis.

Both have the same specifications. Means that from your shown table and it's contents you can not see how the input behaves.

Klaus

 

[keyboardcowboy]

Hi,

There are two different input modes:
* true schmitt trigger behaviour with hysteresis ... what you describe above
* standard input: with "grey area" between HIGH and LOW. Signals in the grey area may (randomly) read as H or L. No hysteresis.

Both have the same specifications. Means that from your shown table and it's contents you can not see how the input behaves.

Klaus

So in order to figure out if there is any hysteresis, I have to check if the input type is of schmitt trigger type or not. Correct?

 

[KlausST]

Hi,

correct.

The SD stanadard does not specify schmitt trigger inputs, afaik.

So for a 3.3V system you should apply:
* less than 0.8V for LOW
* more than 2.1V for HIGH
.. which should be no problem for standard 3.3V CMOS outputs.

Klaus