Internal Stripline

[Smillsey]

Hi all!

I am at the stage of manufacturing a pcb and in discussion witht he pcb fabricator regarding stackup (which they are trying to change, as usual!)

I have a 6 layer pcb, I have used layers as follows;

L1 : SIG
L2 : GND
L3 POWER PLANES
L4 SIG
L5 : GND
L6 : SIG

I set my stackup so that the spacing between 3 and 4 was much larger than the spacing between 4 and 5...

L3 -> L4 space was around 1mm
L4 -> L5 space was around 0.076mm

My theory was to "closely couple" the L4 -> L5, because L5 is a single solid ground plane and will be the return path for L4 high speed diff pairs and singled ended controlled impedance traces...

I wanted the L3 layer to have very limited affect on the impedance of L4, as it is not a single continuous plane....

I may be worried about nothing here, as L5 is a continuous plane and will provide the return path for the high speed signals, but can somebody put my mind at rest that I am okay to work as above? I am sure that as long as the "closely coupled" reference plan is continuous, this will be fine.... But any input would be appreciated

I have attached an example of what i mean.... You can see that the high speed trace passes over gaps in the power plane layer (which is 1mm away from the signal layer in question...) But i feel this will be fine as the ground plane for this trace is continuous and only 0.076mm from the signal traces and in my mind will provide a good return path.

 

[FvM]

I'd generally avoid extreme PCB stackup parameters like you are suggesting. Rather choose balanced substrate and pre-preg thickness.

Specifically, differential pairs don't involve return currents and have less problems with discontinuous reference planes as long as the gaps are small and the lines routed transverse to gap. We however need to know signal kind (analog/digital) and rate to determine tranmission line quality requirements.

 

[Smillsey]

Hi FvM,

thanks for the reply, i see.... but why does it matter about thickness of centre dielectic and dielectric between other layers. It will still be symmetrical...

 

[FvM]

6 layer is usually build from two cores. Thin 76 u cores and 1 mm center prepreg are not optimal.

76 u substrate height also restricts transmission line dimensions an probably involves higher impedance tolerance.

All possible but not preferred.

 

[Smillsey]

ok, i will liaise with the pcb house thanks

--- Updated May 19, 2023 ---

6 layer is usually build from two cores. Thin 76 u cores and 1 mm center prepreg are not optimal.

76 u substrate height also restricts transmission line dimensions an probably involves higher impedance tolerance.

All possible but not preferred.

just clarify one thing for me... if a signal is single ended and will have return currents... will it be fine as long as i have a continuous unbroken ground plane on one side of the signal layer and on my "power plane" layer i do not run the signals along the "breaks" in that power palne?

I have some spi signals that are single ended...

the diff pairs are pcie and usb2.0

 

[marce]

Edge couple diff pairs on a PCB are interesting, and different than diff pairs down a cable... The PCB coupling involves the return path (of course as it is used in the calculations to determine the diff pair width and spacings). DR Howard Johnson explains it better...

Differential Routing

Is it better to route differential traces over/under (broadside) or side-by-side (edge-coupled)? Newsletter v2-30 11/11/1998(by Howard Johnson)

www.sigcon.com

That said, with careful layout a design will work, it all depends on the noise and speed requirements, when doing critical designs all signals run between two contiguous 0V return planes, with top and bottom signals above a contiguous 0V plane. Where possible an unbroken return path is best...