Why the output power of VCO (Oscillator) is so small?

[Alex_Zhan]

Dear everyone,

I have designed a VCO operating at ~60GHz, the DC power at the output net is 14.6dBm, while the power of fundamental wave is only ~27.6 dBm? Does anyone know the reason?

Here is the output power, thanks very much!

--- Updated Mar 9, 2023 ---

~27.6 dBm

-27.6 dBm

 

[BigBoss]

Nobody knows unless you post your schematic and simulation set-up.

 

[dick_freebird]

I have a question. Why is "DC power" given in dBm?

Standing waves could result in a higher output (reading)
than input power perhaps. This can be measurement
artifact as standing waves result from mismatched line
and invalidate the Z=50 assumption, throwing indicated
power (if figured from VRMS or Vp-p) out the window.

That goes to simulation (or bench) setup. You might be
well off to work in the time domain until you demonstrate
all-proper operation, termination, measurement methods.
Many of the other anlyses are too idealized to debug
setup "by eyeball".

 

[Easy peasy]

dBm is relative to 600 ohm

 

[dick_freebird]

Maybe there -is- DC power, like if it wanted a DC blocking
cap but you didn't give it one? Wouldn't think imposing DC
on what should be a ground referred, controlled impedance
RF output, is common or a good idea.

 

[Alex_Zhan]

Nobody knows unless you post your schematic and simu

Maybe there -is- DC power, like if it wanted a DC blocking
cap but you didn't give it one? Wouldn't think imposing DC
on what should be a ground referred, controlled impedance
RF output, is common or a good idea.

Dear BigBoss and freebird,

I use the open-drain buffer to output the signal. This is the schematic of the buffer. For better test, I use single-ended output, and the other port is connected by a 50 Ohms resister.

Besides, I use the biastee for testing, the OP terminal is the port after the buffer. And I use PSS simulation, I plot the spectrum of the power and show the result above. Why?

 

[BigBoss]

For me, nothing is clear. You're showing a weird buffer but I don't understand what's going on ....
Does the problem occur at VCO or Buffer ?? Why you use differential to single ended ?? What is your essential intention ?? What is the mystery in using Open Collector. You're working on 60GHz and R10 14x4 um ??