Unusual gate pulses in LLC converter

[biswaIITH]

Hii ,

I am currently working on an LLC half bridge resonant converter for battery charger application.

Below are the gate pulse we captured on the scope.

Yellow one is for high side mosfet & green is for bottom side mosfet.

Any idea why is there a bump on high side pulse before it turns on.?????

 

[FvM]

How do measure high side gate voltage? Differential probe? Can you show bridge output together with highline gate?

 

[cupoftea]

..Yes feed the LLC thru an isolation transformer, and then view the switching node with a 100:1 probe. (wrt primary ground)
Ie, where drain of low side fet meets source of high side fet.

Also, please also attach both probe ground and clip to the switching node together, and see what it shows.

Are you using PNP turn off?...what is holding your fet off when it should be off?
Do you have high series resistance in the high side gate drive path?

 

[Easy peasy]

Full - detailed - accurate schematic sketch please, also show Vds on the lower at the same time

 

[biswaIITH]

..Yes feed the LLC thru an isolation transformer, and then view the switching node with a 100:1 probe. (wrt primary ground)
Ie, where drain of low side fet meets source of high side fet.

Also, please also attach both probe ground and clip to the switching node together, and see what it shows.

Are you using PNP turn off?...what is holding your fet off when it should be off?
Do you have high series resistance in the high side gate drive path?

Please find the below waveforms

1) Waveform No 1

Vgs(Green), Vds(Blue) top side Mosfet

2) Waveform No 2

Vgs(Yellow), Vds(Blue) bottom side Mosfet
Vgs(Green) -top side Mosfet

3) Waveform No 3

Tank current


The mosfet has an intrinsic gate resistance of 5.2 ohm. Series turn-on resistance for the top mosfet is 10 ohm.

I have tried with 1 ohm gate resistance & found no improvement in High side gate spike

Tank current is below resonance condition & looks peculiar as well

 

[mtwieg]

Some of this may be artifacts from probing, but I'm betting there is a real cross conduction event happening.
Is the scale on Vds correct? 500V/div? Have you checked whether you're violating the CMTI rating of your gate drivers?
Do you see this only at specific line/load conditions?
Adding capacitance or an RC snubber to the bridge might help.

 

[biswaIITH]

Some of this may be artifacts from probing, but I'm betting there is a real cross conduction event happening.
Is the scale on Vds correct? 500V/div? Have you checked whether you're violating the CMTI rating of your gate drivers?
Do you see this only at specific line/load conditions?
Adding capacitance or an RC snubber to the bridge might help.

You mean adding RC snubber between Gate & source??
it is not 500V/div,thats due to incorrect setting of oscilloscope

 

[biswaIITH]

I have attached few more waveforms. In all my tests, I have provided 220ns
HS LS WAVEFORM1
Top side Mosfet gate pulse (green),Bottom side Mosfet (yellow) & Top side Mosfet Vds(Blue).

You can see after the top mosfet is turned off,it takes approx 97 ns for Vds across it to rise to max value. You can see ringing starts only after that & continues for another 121 nsec till the bottom side mosfet is turned on. My thought is after 97nsec bottom side mosfet Coss is completely discharged & it's body diode starts conducting. I deally i can turn on the bottom mosfet at this time. But may be due to some reason it is ringing till the bottom mosfet is turnedon.

Is it happening due to higher dead time ??

Similar waveform is observed when top side mosfet is turned on & bottom side is turned off.

 

[cupoftea]

Please find LTspice sim (free download)...try to set it up as yoru circuit, and do stuff to it to try and recreate your blip.
Put in your circuit values...and transformer L etc..including leakage L...and post it back if you want.
Then we can "see" your problem and try and recreate it ourselves.
Also tell the FET you use so we can see CDS...

Your problem is suggestive of too long deadtime.

 

[biswaIITH]

Please find LTspice sim (free download)...try to set it up as yoru circuit, and do stuff to it to try and recreate your blip.
Put in your circuit values...and transformer L etc..including leakage L...and post it back if you want.
Then we can "see" your problem and try and recreate it ourselves.
Also tell the FET you use so we can see CDS...

Your problem is suggestive of too long deadtime.

Lm= 130uH
Lr= 27uH
Cr=40nF
Transformer turns ratio is 24:4:4

Vin =390 Vdc
Vout = 35-58 V dc
Iout= 12 A
Range of operating frequency is 85-200kHz.
Resonant frequency is 153Khz
Mosfet used is STP33N60M2

 

[cupoftea]

Thanks, ill have a go later, what about any leakage in the txformer?..is it interleave wound?
Do you have the caps split into two 20nF , one to each rail?
Your vout is 66V?
Your vin is 400v?
What gate drive you use?...bootstrap?.....simple two windings on former?.....PNP turn off?

 

[FvM]

Still not clear how the high side gate voltage is measured.

Commutation of the switching node can't generate a positive gate pulse at the HS switch. Either it's a measurement artifact caused by common mode dv/dt or false triggering of the gate driver logic.

 

[biswaIITH]

Still not clear how the high side gate voltage is measured.

Commutation of the switching node can't generate a positive gate pulse at the HS switch. Either it's a measurement artifact caused by common mode dv/dt or false triggering of the gate driver logic.

Gate pulses for top , bottom Mosfets & drain to source voltages are all measured by differential probe with a BW of 25Mhz

--- Updated Mar 7, 2023 ---

Thanks, ill have a go later, what about any leakage in the txformer?..is it interleave wound?
Do you have the caps split into two 20nF , one to each rail?
Your vout is 66V?
Your vin is 400v?
What gate drive you use?...bootstrap?.....simple two windings on former?.....PNP turn off?

Yes it is split as two 20nF.
As it is for battery charging , Vout := 35-58Vdc
Vin = 390Vdc

 

[FvM]

Thanks for the circuit diagrams. I opt for measurement artifact due to insufficient common mode rejection of differential probe.

 

[biswaIITH]

I captured the following waveforms at the input side of the Isolator(U2;- ISO7220) that comes from processor & compared with gate pulses

Below waveform is when power board is off & only control card where processor sits.
High side pulse before isolator :- Yellow
Low side pulse before isolator :- Green
High side pulse at the top mosfet :- Blue
There is a delay of aprox 520 nsec

Below waveform is taken after converter is powered on.

You can see the ringing is happening on the input side of the isolator & it gets reflected on the gate pulse exactly on the same point.

I will probe further into the grounding & come back with test results.

 

[FvM]

You can clearly see that the noise pulse is not actually injected at the isolator input, or if it is, not causing a reaction in the gate circuit which would be respectively delayed. The 10k series resistors might "attract" noise injection nevertheless.

Harder to decide if you have an actual pulse in the gate circuit or if it's a pure measurement artifact. I guess the latter.
In any case, the waveforms are demanding for additional common mode filtering in probing setup. You can think e.g. about big toroid cores for each probe cable and shortest possible ground connection, e.g. using coaxial jacks for probe tips.

 

[danadakk]

Determining optimum Gate R :

https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00068.pdf?did=59460

https://www.ti.com/lit/ml/slua618a/slua618a.pdf?ts=1656526019670

The switching time spec used 4.7 ohms external for this test circuit :

Regards, Dana.

 

[mtwieg]

I think probing issues can explain the waveforms in posts #8 and #15. I'm guessing the high frequency ringing is coming from secondary side commutation.

The waveforms in post #5 (which show the top side FET turning on, as opposed to #8 which has the top fet turning off) still looks a bit suspicious, mainly the lower frequency bump on the green trace. It could just be due to imperfect CMRR on the diff probes. To check, you can swap the probe leads and check the waveform again. If that bump changes polarity, then it's "real". If not, then it's a common mode effect.

 

[biswaIITH]

I think probing issues can explain the waveforms in posts #8 and #15. I'm guessing the high frequency ringing is coming from secondary side commutation.

The waveforms in post #5 (which show the top side FET turning on, as opposed to #8 which has the top fet turning off) still looks a bit suspicious, mainly the lower frequency bump on the green trace. It could just be due to imperfect CMRR on the diff probes. To check, you can swap the probe leads and check the waveform again. If that bump changes polarity, then it's "real". If not, then it's a common mode effect.

I think you & other respected members suspected it rightly. The polarity of ringing is not reversing even after changing probe lead.
I am getting a high CMRR & BW probe to check this & update here in 1-2 days

 

[mtwieg]

Keep in mind that the CMRR of a probe is very frequency dependent. Probes usually highlight their CMRR at DC, but they should also specify CMRR at higher frequencies, including their rated bandwidth. Should double check that when comparing results from different probes.