[SOLVED] ERROR in synopsys: width mismatch on port 'reset' of reference to 'DFF' in 'FIR_Filter' (link 3)

[mohamis288]

Hello,

I have created a FIR_Filter verilog code and I want to synthesize my code in Synopsys software.
But When I want to elaborate my Verilog code, the following Error shown:

What is the problem?

My verilog code is present in the attachment.

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/26/2021 02:24:17 PM
// Design Name:
// Module Name: FIR_Filter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
module FIR_Filter(clk, reset, data_in, data_out);
 
parameter N = 8;
 
input clk, reset;
input [N-1:0] data_in;
output reg [N-1:0] data_out;
 
// coefficients defination
// Moving Average Filter, 3rd order
 
wire [7:0] b0 =  8'b00001010;
wire [7:0] b1 =  8'b00010000;
wire [7:0] b2 =  8'b00101000;
wire [7:0] b3 =  8'b01000000;
wire [7:0] b4 =  8'b00101000;
wire [7:0] b5 =  8'b00010000;
wire [7:0] b6 =  8'b00001010;
 
 
wire [N-1:0] x1, x2, x3, x4, x5, x6;
 
// Create delays i.e x[n-1], x[n-2], .. x[n-N]
// Instantiate D Flip Flops
DFF DFF0(clk, 0, data_in, x1); // x[n-1]
DFF DFF1(clk, 0, x1, x2);      // x[x[n-2]]
DFF DFF2(clk, 0, x2, x3);      // x[n-3]
DFF DFF3(clk, 0, x3, x4);     
DFF DFF4(clk, 0, x4, x5);
DFF DFF5(clk, 0, x5, x6);
 
 
//  Multiplication
wire [N-1:0] Mul0, Mul1, Mul2, Mul3, Mul4, Mul5, Mul6; 
assign Mul0 = data_in * b0;
assign Mul1 = x1 * b1; 
assign Mul2 = x2 * b2; 
assign Mul3 = x3 * b3; 
assign Mul4 = x4 * b4; 
assign Mul5 = x5 * b5; 
assign Mul6 = x6 * b6; 
 
 
// Addition operation
wire [N-1:0] Add_final;
assign Add_final = Mul0 + Mul1 + Mul2 + Mul3 + Mul4 + Mul5 + Mul6;
 
// Final calculation to output
always@(posedge clk)
data_out <= Add_final;
 
endmodule
 
module DFF(clk, reset, data_in, data_delayed);
parameter N = 8;
input clk, reset;
input [N-1:0] data_in;
output reg [N-1:0] data_delayed;
 
always@(posedge clk, posedge reset)
begin
    if (reset)
    data_delayed <= 0;
    else
    data_delayed <= data_in;
   
end
 
endmodule

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[FvM]

Try 1'b0 instead of 0 in DFF instantiation.

 

[mohamis288]

solved. thank you very much.