Why not drive parallel FETs from the same driver?

[cupoftea]

Hi,
This shows paralleled FETs being driven from the same driver (FETs in "direct parallel")...

https://www.analog.com/media/en/technical-documentation/eval-board-schematic/1641asch.pdf

..this is obviously very convenient...however, looking over the schematics of many 300W+ offline SMPS's shows that FETs are never driven in "direct parallel" like that...every FET always has its own driver.

Why is it possible to drive FETs in "direct parallel" in the web link given above?

 

[dick_freebird]

Paralleling the load will degrade edge times, extend the Miller plateau etc. If that doesn't matter to you,then fine. Or if it's beefy enough of a driver to smack around a few gate networks, with those limiting gate peak current-take.

Driver per FET allows tighter G-S current loop in the larger assembly, I expect, than driving N of them spread apart by thermal management.

 

[Easy peasy]

This is a multi-variate question, at higher VDS, there are some fets that simply do not like being hard paralleled - they just go bang ( well one of them does ) due mainly to the low R_internal_gate and the VHF ringing that occurs between the gates.

Fets with higher internal gate R seem to be able to be paralleled with few issues - although external R's and or external very small beads are a good idea also

Lower voltage higher current fets can be quite rugged and can often ( but not always ) put up with internal gate oscillations from being hard paralleled ( more of this for poor layout ) - for tight layouts you some times need a very good scope or current sniffer to see these VHF oscillations - they can just look like a bit of fuzz on the gate rise or fall on a mediocre scope.