Are these three Carry Look Ahead Circuits Equivalent?

[kvn0smnsn]

I've been reading up on carry look ahead adders, and from the diagram on "https://en.wikipedia.org/wiki/Carry.../File:Four_bit_adder_with_carry_lookahead.svg" I've built the following file:

module ClaFour( cOut, sum, aOp, bOp, cIn);
  output        cOut;
  output [ 3:0] sum;
  input  [ 3:0] aOp;
  input  [ 3:0] bOp;
  input         cIn;
  wire   [ 3:0] pro;
  wire   [ 3:0] gen;
  wire   [ 3:0] car;

  assign car[ 0] = cIn;

  genvar bt;
  generate
    for (bt = 0; bt < 4; bt = bt + 1)
    begin
      assign pro[ bt] = aOp[ bt] ^ bOp[ bt];
      assign gen[ bt] = aOp[ bt] & bOp[ bt];
      assign sum[ bt] = pro[ bt] ^ car[ bt];
    end
  endgenerate

  assign car[ 1] = gen[ 0] | cIn & pro[ 0];
  assign car[ 2] = gen[ 1] | pro[ 1] & gen[ 0] | pro[ 1] & pro[ 0] & cIn;
  assign car[ 3]
       = gen[ 2] | pro[ 2] & gen[ 1] | pro[ 2] & pro[ 1] & gen[ 0]
                 | pro[ 2] & pro[ 1] & pro[ 0] & cIn;
  assign cOut
       = gen[ 3] | pro[ 3] & gen[ 2] | pro[ 3] & pro[ 2] & gen[ 1]
                 | pro[ 3] & pro[ 2] & pro[ 1] & gen[ 0]
                 | pro[ 3] & pro[ 2] & pro[ 1] & pro[ 0] & cIn;

endmodule

But then I realized that this is really equivalent to this file:

module ClaFour_Eqv( cOut, sum, aOp, bOp, cIn);
  output        cOut;
  output [ 3:0] sum;
  input  [ 3:0] aOp;
  input  [ 3:0] bOp;
  input         cIn;
  wire   [ 3:0] pro;
  wire   [ 3:0] gen;
  wire   [ 3:0] car;

  assign car[ 0] = cIn;

  genvar bt;
  generate
    for (bt = 0; bt < 4; bt = bt + 1)
    begin
      assign pro[ bt] = aOp[ bt] ^ bOp[ bt];
      assign gen[ bt] = aOp[ bt] & bOp[ bt];
      assign sum[ bt] = pro[ bt] ^ car[ bt];
    end
  endgenerate

  assign car[ 1] = gen[ 0] | cIn & pro[ 0];
  assign car[ 2] = gen[ 1] | pro[ 1] & (gen[ 0] | pro[ 0] & cIn);
  assign car[ 3]
       = gen[ 2] | pro[ 2] & (gen[ 1] | pro[ 1] & (gen[ 0] | pro[ 0] & cIn));
  assign cOut
       =   gen[ 3]
         |   pro[ 3]
           & ( gen[ 2]
             | pro[ 2] & (gen[ 1] | pro[ 1] & (gen[ 0] | pro[ 0] & cIn)));

endmodule

Isn't it? And then I got to thinking, isn't that equivalent to the following
file with (nmBits) set to 4?

module ClaAdd #( nmBits = 4)
              ( cOut, sum, aOp, bOp, cIn);
  output               cOut;
  output [ nmBits-1:0] sum;
  input  [ nmBits-1:0] aOp;
  input  [ nmBits-1:0] bOp;
  input                cIn;
  wire   [ nmBits-1:0] pro;
  wire   [ nmBits-1:0] gen;
  wire   [ nmBits  :0] car;

  assign car[ 0] = cIn;
  assign cOut    = car[ nmBits];

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      assign pro[ bt    ] = aOp[ bt] ^ bOp[ bt];
      assign gen[ bt    ] = aOp[ bt] & bOp[ bt];
      assign sum[ bt    ] = pro[ bt] ^ car[ bt];
      assign car[ bt + 1] = gen[ bt] | pro[ bt] & car[ bt];
    end
  endgenerate

endmodule

So here are three files, that I think do the same thing. Am I wrong? Are any of these slower than the others, and if so, why?

 

[FvM]

At least the third design is no CLA because carry is generated recursively.

assign car[ bt + 1] = gen[ bt] | pro[ bt] & car[ bt];

To compare speed, you'll determine the longest combinational path in each design.

 

[FvM]

An additional comment. Presumed the three designs are logically equivalent, you should be aware that the synthesis tool may implement the gate level logic differently depending on timing and possible structure constraints. Respectively a CLA might be translated to non-CLA due to relaxed timing constraints or vise-versa non-CLA to CLA enforced by restrictive timing.

--- Updated Nov 28, 2022 ---

If the the question refers to FPGA implementation, the answer is partly different. FPGA logic elements have dedicated carry chains that are faster than other logic in- and outputs. Unfortunately, a gate level description as in the example isn't necessarily recognized as adder and doesn't take advantage of the fast carry chain. Adder inference depends on arithmetic operators in HDL code.