praveen1984
Newbie level 5
Hi,
I have a doubt regarding electromigration on nets in VLSI design.
In any SoC design, there are only three nets: the Power/Ground net, Signal net, and Clock net.
My question is which of the net is more prone to electromigration and why?
Please correct me if my question or net assumptions were wrong.
Thank You
I have a doubt regarding electromigration on nets in VLSI design.
In any SoC design, there are only three nets: the Power/Ground net, Signal net, and Clock net.
My question is which of the net is more prone to electromigration and why?
Please correct me if my question or net assumptions were wrong.
Thank You