Logic level translation

[Junus2012]

Hello,

I have a digital signal from a control unit with Logic '1'=4.95 V and logic '0'=1.65 V,
I want to convert it to logic '1'= 3.3 V and logic '0'= 0 V.

My idea to translate this voltage is by connecting a comparator with a supply voltage of 3.3 V, I tie the inverting input to a low voltage like 0.5 V (or any safe low voltage that fall with the input range of the comparator).

The critical case in this idea is when the input voltage is at 4.95 V, which is 1.65 V above the supply voltage of the comparator which is not accepted by many of the comparators I searched. However, I found the LM393LV-Q1 Dual and LM339LV-Q1 from Texas Instruments can handle it

https://www.ti.com/lit/ds/symlink/lm393lv-q1.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1666195493807&ref_url=https%253A%252F%252Fwww.mouser.de%252F

The other problem is when I want to feedback my control unit, in this case, I need to convert the 0, 3.3V to 1.65, 4.95V

The speed is another problem, the LM393LV is limited to maximum toggle frequency of 1 MHz, while I need above 10 MHz.

I searched in logic level translator circuits, but I found those IC works perfectly with respect to ground (0 V), while you see I have 1.65 V in either of the sides.

Thank you for your help in advance

Regards

 

[d123]

Hi,

Inverter maybe, discrete NMOSs with pull-ups to +Vs could be level translators for both directions/supply voltages. Haven't thought much if doable with BJTs. Can't put a Vref for 1.65V pedestal somewhere?

Can't look for pdfs now but remember seeing various embodiments of OA as limiter using Vref (and maybe diodes). Clipper is one term, maybe ideal diode or signal conditioning bring it up as well.

 

[KlausST]

Hi,

Comparator with open collector (open drain) output
Supplied with 5V, don´t forget the bypass capacitor.
Output pulled up to 3V3
Inverting input to 2.5V (5V/2)
signal input to non_inverting input

Finished one direction

***
Other direction:
* analog switch SPDT with TTL level digital input thresholds
* supplied with 5V (bypass)
* logic input to the control input
* NC to 1.65V
* NO to 4.95V
* COM = output

Klaus

 

[danadakk]

Of course you can get these as functional logic parts :

https://www.onsemi.com/products/timing-logic-memory/standard-logic/level-translators

Even tiny gate logic translators :

https://www.ti.com/pdfs/logic/littlelogicsg.pdf

Regards, Dana.

 

[dick_freebird]

If you are allowed some input current, a diode (or two)
and a burden resistor (or current sink) to Gnd, followed
by a Schmitt / Yoo buffer, ought to do the job.

If you have access to the source supply for those signals
then a simple PMOS switch, diode(s) and passive load,
could be done against the 5V rail (presumably your
"4.95V" is really 5V supply and some allocation to voltage
drop / ground skew).

If you had sourceing-5V-supply access and a complementary
signal pair then a cross coupled level shifter would be the
ticket. But if you had to do the inverted phase yourself you'd
want a set of 5V transistors.

 

[Junus2012]

Dear friends,

Thank you very much for your help and suggestion,

with regard to circuit simplicity and loading effects due to use of dioides like freebird suggested, I found Klaus solution is more suitable also thanks to Dana for suggesting links that also lead to switch solution.

The first direction from 4.95 V, 1.65 V to 3.3 V, 0V is solved by the open-drain comparator suggestion.

for 3.3 V, 0 V to 4.95 V, 1.65 V translation, I have found this SPDT analog switch from Texas Instruments,

https://www.ti.com/lit/ds/symlink/tmux1136.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1666196636389&ref_url=https%253A%252F%252Fbr.mouser.com%252F

I can use it to clarify the principle, maybe I switch to other IC due to the packagae type but that is not importnat for the moment. Below please see the connection according to Klaus's suggestion

According to datasheet, the switch control (SEL) is compatible to work even with 1.8 V when the IC is powered by VDD=5 V, hence, it looks perfect to my situation as my control voltage is 3.3 V, 0 V. From my side I see functional block should work for my purpose of 3.3 V, 0 V to 4.95 V, 1.65 V translation.

But I have one concern: during the transition from S1A to S2B, the output will have floated inputs, so I think I have to connect either a pull-up resistor from D1 (other defines it as COM) to 4.95 V or a pull-down resistor to 1.65 V. I want to discuss this issue with you and to select the appropriate value of the resistor.

Thank you all once again

 

[KlausST]

Hi,

There are many, many, many SPDT MUXes.
How to read the datsheet:
* SELx V_IH: 1.49V ...5.5V. thus your 3.3V is well above 1.49V
* SELx V_IH: 0.0V ...0.87V. thus your 0V is well below 0.87V. (Absolute minimum: -0-5V)

* Break before make time: typ 8ns (Mind: don´t use a "make before break" type SPDT)
This means the node is floating for 8ns typically when switching from NC to NO and back. Usually the trace/wire capacitance ensures valid level during this 8ns.
I´d not use a pullup.
In detail it depends on node capacitance and node (leakage) current.

To your drawing (pedantic).
While the nodes 1.65v, 4.95V, 5.0V are constant ... the "3.3V" node is not constant.
To avoide confusion better write "3.3V CMOS", or "3.3V logic", or "3.3V / 0V"

All unused inputs must not be left floating.
and it misses the bypass capacitors. Maybe it´s a good idea to even bypass the 1.65V and the 4.95V nodes (also the 2.5V node).

Klaus

 

[Junus2012]

Dear Klaus,

I am very grateful to you for your help and explanation,

I agree on all the point you discussed, and here is the simplified block digram of the system that I am working in.

The DC level shifting is required to make the Red Pitaya FPGA compatible to our CMOS chip under test.
I mean compatible is main due to the internal ADC of the FPGA board is referenced and fixed to ground (0 V), while our chip is a single supply operation powered by 3.3 V. Hence we want the shift to match to convert the 0 level of the red pitaya to 1.65 V when writing data to the chip, vice versa we do when we want to read data from the chip.

With regards to this condition, what is the maximum frequency that the selected SPDT can go? can I calculate it from this formula

fmax=1/(transition time+settling time)

The transition time is given by the data sheet as about 19 ns but at their load condition for the VDD= 5 V.

Thank you once again

 

[KlausST]

Hi,

what is the maximum frequency that the selected SPDT can go?

maximum frequency: Yes, I guess this is according your formula.

but...

when we want to read data from the chip.

For read/write this frequency is useless. You nned to do a timing analysis for the complete communication path.
No one can tell you.

****
You talk this all is bacuse of ADC...
Then I´d rather go with a common GND and shift the analog signal.
Mainly because "GND" should be the reference for all voltages. Isolating GND may reduce overall performance by introducing noise.
In detail it dependson the application´s requirement.

Klaus

 

[Junus2012]

Dear Klaus,

Thank you again for your useful information and help.

You talk this all is bacuse of ADC...
Then I´d rather go with a common GND and shift the analog signal.
Mainly because "GND" should be the reference for all voltages. Isolating GND may reduce overall performance by introducing noise.
In detail it dependson the application´s requirement.

This option is still available for us, we didn't ignore it completely. Some issue we have with it but I will post it in different post to reduce the stress on this post.

I am back to you again with this open-drain opamp, MCP6546

https://www.mouser.de/datasheet/2/268/21714G-278008.pdf

The data sheet is only referring to the open drain to be connected to the voltage level (VUP) that is higher or equal to VDD,

In my case you know I have VDD=5 V and need to connect the VUP to 3.3 as per your suggestion. Is there any real restriction preventing me from connecting VUP to 3.3 V for this device? or it is only a matter of how they characterized it.

It will be useful for me to know about this issue regardless I can have an alternative comparator. Also the MCP6546 is fetting to my other demand specifications.

Thank you in advance

Regards

 

[KlausST]

Hi,

I am back to you again with this open-drain opamp, MCP6546

I like to differ between OPAMP and comparator.
MCP6546 is a comparator (OPAMPs usually don´t have open drain output)

The data sheet is only referring to the open drain to be connected to the voltage level (VUP) that is higher or equal to VDD,

The given datasheet says:
Output Pull-Up Voltage: 1.6V ... 10V. (don´t know why not specified down to 0, maybe because of internal hysteresis)
... but 3.3V is within specified range

Klaus

 

[FvM]

Looking at the post #8 schematic, I wonder why the two 3.3V supply voltages have been shifted against each other in this unsual way. The schematic doesn't show a detail that would require the offset. But may be it's hidden in the schematic.

 

[Junus2012]

Thank you Klaus, that was a mistake I typed opamp , thank you for the correction and for confirming me the data sheet.

Looking at the post #8 schematic, I wonder why the two 3.3V supply voltages have been shifted against each other in this unsual way. The schematic doesn't show a detail that would require the offset. But may be it's hidden in the schematic.

Thanks, FvM. yes it is an unusual way, it is the first time for me to shift a system like this way but surprisingly it is working

We shifted the FPGA board ground to 1.65 V so it can fit to our single supply chip. The red pitaya board simplify our test cause it has internal ADC, DAC, ADC drivers, and a programmable function generator but all referenced to ground.

Shifting the ADC ground to 1.65 V however will also shift all the FPGA ground to 1.65 V, hence we needed the logic translators between the DUT and the FPGD board.

To tell you more story, we are able to use an external fast sampling ADC as a logical solution that it comes to mind, that even was my topic in another post, but you know fast sampling ADC for our application requires a parallel interface of at least 14 bits we need. The red pitaya board has only 16 GPIO, hence it will be mostly consumed by the ADC and nothing remaining for the chip control.
At this point you may advise to buy another FPGA board with larger GPIO and solving the system regularly with an external single supply 3.3 V ADC , I would say here this option we didn't dump it but we currently want to run the things on what we have, and we have 5 red pitaya boards