How back to back inverter matches skew in clocks

[sneha rayala]

Hi , I was working on single ended to differential clock circuit and couldn't understand what exactly is happening with the back to back connected inverters (please look at picture posted below )how are they matching the skew between clocks and what is contention there ? Please provide a thorough explanation, complete with figures.and if available kindly share any documents or papers on this.

 

[KlausST]

Hi,

the schematic doesn´t seem to be correct:
There twice are outputs of inverteres directly connected, So the outputs fight against each other.
Not clear which one will win.
Also short circuit current may kill one or several inverters.

--> give a link to the original schematic or document.

Klaus

 

[sneha rayala]

Hi,

the schematic doesn´t seem to be correct:
There twice are outputs of inverteres directly connected, So the outputs fight against each other.
Not clear which one will win.
Also short circuit current may kill one or several inverters.

--> give a link to the original schematic or document.

Klaus

Hi , the schematic was given to get a basic idea of application but my main intention was to know about transient behaviour of the back to back connected inverters when there is skew between the input and outputs how interpolation is done .

 

[dick_freebird]

The cross coupled inverters add positive feedback/hysteresis and sharpen the edge (after fighting it initially) and somewhat binds the two phases together.

IME that "1 vs 2" delay will not get as right, as a "loaded 2 vs 3" matchup.

 

[d123]

Hi,

Must ask... Why 1 + 2, but 2 + 3 better, and not e.g. 2 + 2 or 3 + 3, using a non-inverting buffer on the CLK side to even up switching transition times? Is it better that CLK always changes state one (tpropagation delay + tr + tf) faster than !CLK) or vice versa) or preferable that they change state at the same time? Is a delay set that way to prevent shoot-through or undefined state battle?

 

[KlausST]

Hi,

without additional information I have to assume that all inverters are identical.
If all inverters are identical then the circuit can not work at all.

Klaus

 

[d123]

Hi Klaus,

Why? Do you see it only oscillating? I understand the idea behind the circuit and can't decide whether it either would be unstable and oscillate or flatline to a fixed state forever on both outputs, or does actually make sense and work because the complementary input signals reinforce what is happening on the other side (side meaning CLK and !CLK). It brings back (not so good) memories of breadboarding 'great ideas with logic gates (that don't work)' a few years ago - not to say I don't see sneha's circuit as a credibly viable design, because I think I do, so I'm interested in why you say it can't work.

 

[KlausST]

Hi,

I expect fixed state.
two (identical) inverter outputs fighting each other. Why should it change state?

Klaus

 

[FvM]

without additional information I have to assume that all inverters are identical.
If all inverters are identical then the circuit can not work at all.

I'd think the other way. Assuming that the circuit serves a purpose (adding hysteresis, as said) the "back-to-back" inverters have to be weaker than the input buffers.

Regarding behaviour with intra-pair delay skew, why don't you check yourself in a simulation? My expectation for resonable drive strength ratio is, that skew will be either kept or slightly reduced.

 

[d123]

Hi,

Intetesting. What/Why? Because e.g. both would be trying to sink at the same time? I (naively, maybe) see it as workable because even at power-up, as CLK will be low for nano- or micro-, etc. seconds, and therefore both inputs will see 0V/low (so CLK will go high, as soon as it can), then after each respective stage's transition times after the inputs decide where they sense the outputs should be, the two inputs (CLK and !CLK) will see opposing level signals. But then at initial power-up, every inverter will 'see' 0V/low... (?)

 

[KlausST]

Hi,

Assuming that the circuit serves a purpose (adding hysteresis, as said) the "back-to-back" inverters have to be weaker than the input buffers.

the OP needs to give some more information.

One could do a simulation. But without additional information .. what drive strength should we choose?
1:1? 1:3? 1:10?
Any information could help to give good answers.

Or added resitors... could help.

But just showing 5 identical inverters will lead to random results.

Klaus

--- Updated Oct 3, 2022 ---

both would be trying to sink at the same time?

if both try to sink .. no problem
if both try to drive HIGH .. no problem.

but to change state: one has the state before, the other has the opposite state.
One inverter input is HIGH, the other inverter´s input is LOW, both outputs are connected. What will the common output be? HIGH or LOW? Why?

Klaus

 

[FvM]

Take a look at transistor-level CMOS ST gate schematic, the concept of positive feedback implemented by weak cross coupled gates is just obvious.(*) With fully driven input, the main data path wins of course.

(*) Standard ST gates use slightly different transistor configuration with separate N and P path for feedback, but the basic function is quite similar. Also smaller transistors for the feedback path.

 

[dick_freebird]

It is not smart to assume identical inverters. To my eye they
look just like the "bus hold" scheme and the cross coupled
will be sized smaller than the forward path inverters.

Still you have the fundamental difference in prop delay sum.
A noninverting buffer is always two inverters. So there is a
one gate delay (give or take delay asymmetry) difference to
be made up.

Many times I have used the "2, loaded vs 3" scheme to make
a complementary, aligned clock (don't say differential when it's
bang-bang logic taking two separate paths). Adding lag to the
noninverting branch can align the outcome (helps if the inverters
are made with equal HL and LH delay and risetime, and your
foundry likes to run on TT center point).

I never examined what (if any) benefit adding the cross coupled
"squaring" might deliver; maybe you could merge the two ideas
and get some added degree of process resilience / tightness of
edge align across PVT.

 

[KlausST]

Hi,

It is not smart to assume identical inverters.

I agree.
But then: Why not visualize it? .. maybe with some series resistors or a "ratio" value.
I understand that this is a key parameter for the circuit. And this is important information, especially for people who want to understand the circuit, who want to learn how to design it properly.

If you give the above circuit to a couple of people and tell them to simulate it.
I guess every simulation will show very different results. From "frozen output" to "useful" to "no benefit".

With some additional information you still will not get 100% identical results, but the basic function will be the same.
In best case you do a parametric simulation to show the influence of the "drive ratio". For an experienced digital designer it may be obvious. But I guess the OP is not yet that experienced.

****
Maybe my view is "too much" like analog design....
I see a comparator with some resistors ... one of them is used as positive feedback.
And the value of this feedback resistor has big impact on circuit function.
* it may influence the comparator about zero
* it is able to adjust hysteresis
* but it may make the circuit to freeze

Klaus

 

[BradtheRad]

To make a workable system, resistors should be added around the cross-coupled inverters. Specifically, to their inputs and outputs in order to add hysteresis.