Varying Verilog code simulation results in "Xilinx Vivado" compared to "Xilinx ISE"

[FlyingDutch]

Hello there,

I wrote Verilog code for implementing "LPC protocol"(Low Pin Count Protocol) driver. And this code works fine in simulation. There was "LPC Host" which sends data over a 4-bit LAD bus and signals Reset and LFRAME (start of LPC frame - cycle) and "LPC Peripheral" which is connected to Host. First I have only I/O cycles support in the project and on simulation (test bench brings "LPC Host" and "LPC Peripheral" to life) and it works fine. Now I want to check if "LPC Peripheral" ignores other cycle types (eg Memory R? W, DMA, etc.). For this purpose, I implemented additional support for "Memory R / W" cycles in "LPC Host" without changing "LPC Peripheral". I also made the required changes to the test bench.
Now I come to the heart of my problem: "When I simulate Verilog code in "Xilinx Vivado 2019.1" the results are perfectly correct (as expected), but if I simulate the same code in Xilinx ISE - the results are very different and incorrect."
I checked also a simulation of this code in an open-source Verilog simulator called "Icarus Verilog" (see link: Icarus Verilog), and the results also were bad and similar to those in "Xilinx ISE".
Could someone more experienced explain to me what could be the reason for this behavior of the simulation? I am not sure if my design is working properly and checking on the FPGA kit, in this case, can be difficult for several reasons.
I attached source files of my project (in zipped archive)
1) lpc_host.v
2) lpc_periph
3) lpc_defines.v (constants used in the design)
4) lpc_periph_tb.v (this is test bench)

Thanks in advance and Regards

--- Updated Sep 4, 2022 ---

Hello,

BTW: I am asking out of curiosity: has anyone encountered such a case where simulating the same code in different environments gave different results?

Best Regards

--- Updated Sep 4, 2022 ---

Hi,

no one has encountered such a situation and can not help. Maybe at least some hints or guesses.

Best Regards

 

[dpaul]

looking at src codes needs a lot of time and motivation!
Perhaps you could post screenshots of simulations to highlight the differences and explain what is going on and what you expect. It might be faster.

 

[FlyingDutch]

looking at src codes needs a lot of time and motivation!
Perhaps you could post screenshots of simulations to highlight the differences and explain what is going on and what you expect. It might be faster.

Hello @dpaul,

thank you for your answer. Have you ever run into such a problem? Maybe the answer to what could potentially be the cause of such a problem will be simpler. After a few experiments, I have a suspicion that the reason is the support of the newer Verilog standard in Vivado compared to ISE. Do you think it might be likely?

Thanks and regards

 

[barry]

we could make guesses all day long. I, too, am not going to waste a lot of time wading through your entire project.

Maybe it’s different versions of IP you’re using? Maybe youve got uninitialized registers?

Perhaps you can just identify WHAT is exactly different. Your question is kind of like saying “my car is acting weird”.

 

[FlyingDutch]

we could make guesses all day long. I, too, am not going to waste a lot of time wading through your entire project.

Maybe it’s different versions of IP you’re using? Maybe youve got uninitialized registers?

Perhaps you can just identify WHAT is exactly different. Your question is kind of like saying “my car is acting weird”.

Hello @barry,

I will try to present here the simulation results for these two environments (Vivado and ISE), but it will take some time.

Thanks and regards

 

[ThisIsNotSam]

I would only add not to pay attention to Icarus, it is not a golden simulator by any standard...
If you have access to Xcelium or VCS, those could be used with confidence that the results are reliable.

 

[TrickyDicky]

Another point to note - ISE has not received any updates for 8 years. The vivado version you are using is 3 years old, but you could be using a newer version. Xilinx simulators have never had a good reputation.

 

[FlyingDutch]

Hi,

The reason for the error was that I added two new states (constants in the 'lpc_defines.v' file). These constants had the following values:

`define LPC_ST_CYCTYPE_MEMORY_RD   5'h20  //LPC Memory Read (new)
`define LPC_ST_CYCTYPE_MEMORY_WR   5'h21  //LPC Memory Write (new)

They needed 6 bits, and I assigned them to a 5-bit signal. The difference in the simulation was due to Vivado cutting these values down to five bits and ISE and Icarus not.
But it was my error, in fact, each of the simulators behaved properly.

Thanks all for your answers and interest.
Best Regards