The relationship beetween Ids and Vbs in Bulk-Driven Currnet Mirror

[VictorWu]

The author of the paper Wide Current Range and High Compliance-Voltage Bulk-Driven Current Mirrors: Simple and Cascode wrote that “Concerning the output transistor M2, if the output voltage (drain of M2) rises, the output current starts to increase. As a result, bulk of M2 (also M1) increases which in turn makes the gate voltage to decrease, the output current then decrease to the original value.”
I don't know why. I would really appreciate it if someone could explain it for me!

 

[d123]

Hi,

If question is related to bulk-related stuff (you mean about transistor design), no idea.

I'm sure you know that it's just an OA current source (sink): I-in is Vref, so if I-out doesn't match voltage of Vreg, OA will drive gates more or less to see no voltage difference at its inputs.