[SOLVED] Serializer

[stark43]

Hello, I want to send parallel data to my serializer module (by bit shifting) and after serializing the incoming data once, I want it to stop until the other data arrives and not serialize the same data again. If I build a combinotional circuit and do it this way, I guess if my data does not change, it will not re-serialize and this will not work correctly.

always(data_in)
begin
        // serialization operation
end

For example, I know that if 0x23 data comes in consecutively, it will understand as if the data has not changed, because combinational always blocks are entered when there is a change. What is the suggested solution for this?

 

[KlausST]

Hi,

I guess you need to read about basic of serial data transfer.
We can not know what your requirements are, nor can we replace school.

It´s nothing new.
And there are many solutions (serial interface standards).
Some may fit to your application, some may not.

First of you all you need to read about those topics:
* serializer deserializer basics
* asynchronous transfer (UART, IrDa, RC5...)
* synchronous transfer (SPI, I2C ...)
* Baud rate / data throughput
* DC free for transformer coupled systems (like Ethernet, manchester encoding)
* clock recovery (SERDES)
* frame, frame sync
* and so on..

No need to reinvent the wheel. All is done before. All is well documented.
Use internet search, Wikipedia, youtube....

Then come back with more detailed questions.

Klaus

 

[FvM]

As for the Verilog coding aspect, sensitivity lists have no effect in synthesized combinational hardware.

A hardware serializer could look like the corrected code in your previous thread https://www.edaboard.com/threads/basic-serializer-verilog.402007/
Comparison for changed data needs a clock and a register to store the previous value, it could be supplemented to the serializer code. Consider that a receiver must be able to synchronize to the serial data frame, respectively there must be an unequivocal frame start criterion, e.g. a start bit or pattern.

 

[stark43]

As for the Verilog coding aspect, sensitivity lists have no effect in synthesized combinational hardware.

A hardware serializer could look like the corrected code in your previous thread https://www.edaboard.com/threads/basic-serializer-verilog.402007/
Comparison for changed data needs a clock and a register to store the previous value, it could be supplemented to the serializer code. Consider that a receiver must be able to synchronize to the serial data frame, respectively there must be an unequivocal frame start criterion, e.g. a start bit or pattern.

I am using asynchronous FIFO structure. I need to serialize the data I read (1 byte) and for that I thought I should use counter (8 loops). I may not always want to serialize data, or I may want to serialize other data (bundle header, package footer, payload, etc.). I'm considering shifting bits as a basic method for this. I wanted to consult with you on what is the best method for this. I have the line valid and frame valid signals as you said before sending the payload to the serializer module. I think that I need to serialize when my FIFO module sends data rather than initiating serialization when my serializer module detects these signals. I mean, it would be nice if my serializer module could auto-serialize when there is data entry, and stop the serialization process when there is no data entry, I wonder how it is. Otherwise, I will make a valid variable for each incoming data and have it checked.

 

[dpaul]

You need this structure:

incoming parallel data --> Async FIFO --> 8 bit register --> shift out each bit from the register on each clock cycle so that parallel to serial conversion is achieved

When do you read our from the AsyncFIFO? --> Whenever you have ATLEST 8 bits written to it (assumption : FIFO width is 8 bits, depth of the FIFO needs to be decided based on your write clock and read clock values)

So in 1 clk cycle you read out the 8bits from the FIFO and in the next clock cycle these 8 bits are written to the register. Then you need 8 clock cycles more to shift-out these 8 bits one-by-one. Note that until all 8 bits are COMPLETELY shifted, your FIFO should not be read. Continue this cycle until the FIFO is empty. When FIFO is empty, you design should just wait until 8 bits are written again.
Implement this in RTL and your design is done!