vlsi_design2
Member level 1
Hi,
T lines no matter how long they are, if properly terminated with ZL=Z0=R, always presents a resistive load and no capacitive load. Instead if I use a long trace of line of comparable dimension I get a huge capacitor with the substrate (say). Is there an intuitive way to understand this? or the best way is to rely on theoretical formula of Zin = f(Z0,ZL,tan(beta*l)) where once we substitute Z0=ZL, we see pure resistive input impedance?
How the huge cap magically disappears?
T lines no matter how long they are, if properly terminated with ZL=Z0=R, always presents a resistive load and no capacitive load. Instead if I use a long trace of line of comparable dimension I get a huge capacitor with the substrate (say). Is there an intuitive way to understand this? or the best way is to rely on theoretical formula of Zin = f(Z0,ZL,tan(beta*l)) where once we substitute Z0=ZL, we see pure resistive input impedance?
How the huge cap magically disappears?