Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

error on bad component subtype deep n-well NMOS

Status
Not open for further replies.

allennlowaton

Full Member level 5
Full Member level 5
Joined
Oct 5, 2009
Messages
247
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Location
Taiwan
Activity points
3,081
Good day friends,

I would like to ask help regarding this error from the layout.
I using TSMC 0.18um 1P6M process.
My design requires an NMOS with a shorted source and bulk.

Thank you.
 

Attachments

  • bad component subtype.jpg
    bad component subtype.jpg
    119.8 KB · Views: 398

Good day friends,

I would like to ask help regarding this error from the layout.
I using TSMC 0.18um 1P6M process.
My design requires an NMOS with a shorted source and bulk.

Thank you

I also have this error.
The type or subtype of the device is not recognized.

I did try to match extracted device with the netlist file.
and it works for me!

Cheers!

smile.png
 
If you put NMOS in a DNW/VNW pocket then its body is cut
off from the bulk / handle Psub and you will have to route the
body (tap) explicitly to open field and a ptap there.

What value do you imagine putting it in a DNW pocket is,
when you intend to jumper it to the substrate in the end?
You eat a lot of layout area for nothing (except perhaps
substrate noise control).
 
If you put NMOS in a DNW/VNW pocket then its body is cut
off from the bulk / handle Psub and you will have to route the
body (tap) explicitly to open field and a ptap there.

What value do you imagine putting it in a DNW pocket is,
when you intend to jumper it to the substrate in the end?
You eat a lot of layout area for nothing (except perhaps
substrate noise control).
Thank you for the feedback.
My application requires the shorted source and bulk NMOS that will avoid the body effect.
 

So then you do not want source tied to "bulk" (which is the
handle Psub / Pepi) but the local body "pocket" (Pepi inside
DNW/VNW). That may want you to use a 4T FET symbol and
wire it explicitly; the 3T may have an inherited sub! connection
that you either can't modify or can't find?

P- inside DNW is not the same "node" as sub!.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top