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Good day friends,
I would like to ask help regarding this error from the layout.
I using TSMC 0.18um 1P6M process.
My design requires an NMOS with a shorted source and bulk.
Thank you
Thank you for the feedback.If you put NMOS in a DNW/VNW pocket then its body is cut
off from the bulk / handle Psub and you will have to route the
body (tap) explicitly to open field and a ptap there.
What value do you imagine putting it in a DNW pocket is,
when you intend to jumper it to the substrate in the end?
You eat a lot of layout area for nothing (except perhaps
substrate noise control).