Back annotate the extracted parasatics from layout to schematic

[Junus2012]

Hello,

After performing the layout exctraction step, the parasatice elements I can see it on the cell of the extracted view,

These elements are distributed everywhere and it is difficult to debug the circuit with regard these parasitics.

I am wondering if there is a tool that back annotates parasitic elements to the origional circuit schematic?



I am using Cadence Virtuoso version IC6.18-64b-500 and Assura tools


Thank you in advance

Best Regards

 

[Dominik Przyborowski]

Don't know if assura has it, but pvs provides schematic probes to read parasitic elements. Under menu launch->plugins->pvs->parasitic.
Old Diva tool was provided back annotation as labels on the schematic, so assura should have sthing similar. What user guide is saying about this?

 

[timof]

Back-annotating parasitics to the schematic may help you run post-layout-like simulations faster, but may not help you debug the root causes of parasitic issues - i.e. what net, layer and polygon(s) are causing you a trouble.

First question to you - do you need this (back-annotation) to be able to run circuit simulations accounting for parasitics, or is your primary goal - to identify and exterminate the root causes of parasitics problems?

Each company has its own set of scripts and tricks for parasitics debugging.
You can follow them, or you can use commercial tool to do that for you.

Our company, Diakopto Inc., developed an EDA tool, ParagonX, specifically to help debug parasitics problems, you can read more here:

Circuit simulation and parasitics: do we need more speed, or more insight (or both)?

I recently read John Cooley’s interesting article on the Troublemakers panel discussion at DAC 2020 between Mentor’s Joe Sawicki and Cadence’s Anirudh Devgan. They were talking about Mentor’s AFS-XT SPICE simulator beating Cadence’s Spectre-X in speed by a factor of 3x-10x.

www.linkedin.com

Ansys ParagonX | IC layout parasitics analysis and debugging software

ParagonX lets IC design engineers shift left to quickly explore and find the root causes of parasitic-induced design issues.

diakopto.com

 

[Junus2012]

Don't know if assura has it, but pvs provides schematic probes to read parasitic elements. Under menu launch->plugins->pvs->parasitic.
Old Diva tool was provided back annotation as labels on the schematic, so assura should have sthing similar. What user guide is saying about this?

Thank you Dominik for your reply,

I have also PVS installed on my Cadence, but I am using the Assura,
indeed my team leader never told me about the PVS tool and it is interesting to know from you why you prefer it.

Last time I talked to him he advised me to use the "Parasitic Aware Design (PAD) Flow" as well

--- Updated Feb 16, 2022 ---

Back-annotating parasitics to the schematic may help you run post-layout-like simulations faster, but may not help you debug the root causes of parasitic issues - i.e. what net, layer and polygon(s) are causing you a trouble.

will it give the same result as simulating with the extracted view ?

First question to you - do you need this (back-annotation) to be able to run circuit simulations accounting for parasitics, or is your primary goal - to identify and exterminate the root causes of parasitics problems?

My intention is both of them

Each company has its own set of scripts and tricks for parasitics debugging.
You can follow them, or you can use commercial tool to do that for you.

Our company, Diakopto Inc., developed an EDA tool, ParagonX, specifically to help debug parasitics problems, you can read more here:

Circuit simulation and parasitics: do we need more speed, or more insight (or both)?

I recently read John Cooley’s interesting article on the Troublemakers panel discussion at DAC 2020 between Mentor’s Joe Sawicki and Cadence’s Anirudh Devgan. They were talking about Mentor’s AFS-XT SPICE simulator beating Cadence’s Spectre-X in speed by a factor of 3x-10x.

www.linkedin.com

Ansys ParagonX | IC layout parasitics analysis and debugging software

ParagonX lets IC design engineers shift left to quickly explore and find the root causes of parasitic-induced design issues.

diakopto.com

Thanks for the link, i read it and I enjoyed the article, unfortunately I am restricted to work with Cadence tools only

 

[dick_freebird]

I have seen schematics in which this had been done, but have
not done it myself to know the steps.

A concern can be the "double counting" of extracted parasitics if
you use the "wrong" model branch (presuming there is one) -
I've seen RF CMOS flows' PDKs that "keep two sets of books",
a model set for schematics based simulation in which the FETs
have full overlap / adjacent capacitances and maybe even
runt inductors, and a model set which expects these to be
carried in all those pacpacitors and so reduces the intra-FET
cXYo params to achieve a godo match between schematic
predicted, and layout extracted frequency response.

If you push all the extracted Cs into the schematic, then it
probably wants the "post-layout model chain" (if there is).

You likely want to "refine" and drop any sub-fF capacitors as
there's a lot of them and they mean nothing except netlist
bloat and run-time baggage.