Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

D-flipflop question

Status
Not open for further replies.

Justin Wenger

Newbie level 5
Newbie level 5
Joined
Sep 18, 2021
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
88
I was trying to build a frequency divider by using a D-flipflop.

The input frequency is 500MHz, and the expected output frequency was 250MHz. But the output node is not oscillating..

What could be the problem of this circuit?

Thank you.
 

Attachments

  • d-flipflop.png
    d-flipflop.png
    11.8 KB · Views: 127
  • result.png
    result.png
    49.6 KB · Views: 121

It will neither work as a D-FF at 500 kHz, because it's no valid FF circuit.
--- Updated ---

Your circuit is a D-latch. A D-FF would be comprised of two D-latches with one driven by an inverted clock.
--- Updated ---

Alternative you can make a D-FF of 3 RS-latches

1636543395882.png
 
Last edited:
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top