[SOLVED] 4 bits serial in/parel out register in verilog

[nick_20]

hey!! can someone provide me with the behavioral description code of a 4-bit shift register with a serial input and and parel output in verilog
i am looking for something like this**broken link removed**

 

[kirill]

hi

parameter shift = <shift_length>;
reg [shift-1:0] <reg_name>;
always @(posedge <clock>)
<reg_name> <= {<input>, <reg_name>[shift-1:1]};
assign <output> = <reg_name>;

 

[nick_20]

hi

parameter shift = <shift_length>;
reg [shift-1:0] <reg_name>;
always @(posedge <clock>)
<reg_name> <= {<input>, <reg_name>[shift-1:1]};
assign <output> = <reg_name>;

can you elaborate a bit more cause i am dummy????:lol:

 

[kirill]

another example better:

module shift_register (Clk, Clear, SerialIn, ParallelOut);
input Clk, SerialIn, Clear;
output [3:0] ParallelOut;
reg [3:0] tmp; <-- your four flip-flops

always @(posedge Clk)
begin
if (Clear)
tmp <= 4'b0000;
else
tmp <= {tmp[2:0], SI}; <-- concatenation , 1 cycle : you have 1101, 2 cycle : 101+serial in data 2 cycle, 3 cycle : 01+serial in data 2 cycle + serial in data 3 cycle and so on.
end

assign ParallelOut = tmp;

endmodule