4 bit binary counter in FPGA (using VHDL)

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counter in FPGA

Hi sanjana,
as u have solved it, u can just put the way u did to resolve the Exact problem, so that in future others will have some reference when they face the same
 

Re: counter in FPGA

try to declare count as register instead of signal and check.. just try this...
 

Re: counter in FPGA

I used the debounce code given above for the clock and it worked.
 

Re: counter in FPGA

i have a question in counter.
in quartusii,the
reg [3:0] a;
a<=a+1 ;
will have a warning:give the 5bit value to the 4 bit variable.
how to cancel the warning? thank you.
 

counter in FPGA

I don't have that compiler, but I can make a guess. It may be warning you that a<=a+1 will overflow if "a" equals 15. You may be able to avoid the warning by using a 4-bit 1: a<=a+4'd1;
 

Re: counter in FPGA

your advise is good ,the warning in quartusii haven't been seen,but in the synplify,the warning is still there:ignored carry sum.
 

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