4-bit binary adder and subtractor spartan 3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity zbrajalo is
port
	(
	an0 : inout std_logic;
	an1 : inout std_logic;
	an2 : inout std_logic;
	an3 : inout std_logic;
	btn0: in std_logic;
	a: in std_logic_vector (3 downto 0);
	b: in std_logic_vector (3 downto 0);
	led : out std_logic_vector (7 downto 0)
	);
end zbrajalo;

architecture Behavioral of zbrajalo is

begin
process (btn0)
variable s : std_logic_vector (4 downto 0):="00000";
begin
		if(btn0='1') then
			s:=a+b;
			if(an0='0') then
				if(s(1)='0') then
					an0<='1';
					led<="00000011";
					an1<='0';
				elsif(s(1)='1') then
					an0<='1';
					led<="10011111";
					an1<='0';
				end if;
			elsif(an1='0')then
				if(s(2)='0')then
					an1<='1';
					led<="00000011";
					an2<='0';
				elsif(s(2)='1') then
					an1<='1';
					led<="10011111";
					an2<='0';
				end if;
			elsif(an2='0')then
				if(s(3)='0')then
					an2<='1';
					led<="00000011";
					an3<='0';
				elsif(s(3)='1') then
					an2<='1';
					led<="10011111";
					an3<='0';
				end if;
			elsif(an3='0')then
				if(s(0)='0')then
					an3<='1';
					led<="00000011";
					an0<='0';
				elsif(s(0)='1') then
					an3<='1';
					led<="10011111";
					an0<='0';
				end if;
			end if;
	end if;
end process;
end Behavioral;