Clarifications on PushPull Transformer Design

[sabu31]

Hi All,

I am designing a transformer for push pull converter. On going through literature I am having certain confusions

a) The method of calculation of Primary turns. I have seen three equations. When using mathcad I am getting different answers

(i)\[ \begin{equation} N_p=\frac{V_{dcmin}*D_{max}*T_s}{2*B_{max}*A_c}\\ N_p=\frac{V_{dcmin}*10^4}{F*2*B_{max}*A_c*K_f} \end{equation} \]

I am getting two different answers for turns.

b) Is the Turns calculated say N_p=4 is for first half of centre tap or it is total turns and each half wind is 2 turns each.

c) WHat is value of secondary RMS winding currents

I have seen two different answers.
The first one is

\[ \begin{equation} I_{s_{rms}}=I_o\sqrt{D}\\ I_{s_{rms}}=I_o\sqrt(1+D) \end{equation} \]

which one of the two is correct.

 

[treez]

Remember with a pushpull the primary is in two halves which are pulsed alternately.
The secondary is either one coil with FB rectifier, or 2 coils...one for each primary.
In some ways, the pushpull is actually like two one transistor forward converters interleave switched.

To design a push pull transformer, first design a virtual buck converter with your vout. Decide what is your max duty cycle (say 0.7).
So you then design a buck with whatever vin gives your vout with your chosen D.
Then think about that “virtual” vin value.
That virtual vin is what you must get out of your transformer when it has your minimum actual vin at its primary side.

So you then do the transformer equation vpri/vsec = Npri/Nsec
….thats pretty much it.
If you are wondering about how many turns exactly to use, and what exact core etc, and you want an exact formula which spits out everything for you in one go then this is the wrong field for you……you have to do it iteratively and you converge to the solution.
But this is good as it enables you to use your artistic side.
And its very quick in an excel template, which you can easily make up.
You can use any core or wire you like as long as………………..
Solution is not too big
Wire loss not too high
Core loss not too high
Coupling not too poor.
Dont have too much magnetising current
Skin effect is accounted for
You can physically terminate the wire to the former pins.
You dont saturate the core.
Etc etc etc….

If you are using an integrated (PCB) transformer, then try that software that allows these to be effectively designed.

 

[Easy peasy]

For a square wave applied to a standard push-pull transformer dB/dt = V / N. Ae, this is true for input or output, remember you have to add the diode drop to the desired output voltage.

If the Bpk in the Tx is 100mT say, then dB will be 0.2 in the above, as the flux swing dB is from -0.1 to +0.1

dt is the max on time, often this is 48% of the half period, Ae is the core area in m^2

The rms of a pulsed square wave is indeed I x SQRT ( D), so for D = 50% Irms = I x 0.707, and for D = 1, Irms = I

 

[sabu31]

For a square wave applied to a standard push-pull transformer dB/dt = V / N. Ae, this is true for input or output, remember you have to add the diode drop to the desired output voltage.

If the Bpk in the Tx is 100mT say, then dB will be 0.2 in the above, as the flux swing dB is from -0.1 to +0.1

dt is the max on time, often this is 48% of the half period, Ae is the core area in m^2

The rms of a pulsed square wave is indeed I x SQRT ( D), so for D = 50% Irms = I x 0.707, and for D = 1, Irms = I

So this N represents entire winding or half of it.

 

[treez]

If you give me your push pull spec, ill do a transformer for you, and post it here, with all details.
..if you provide, vin, vout, pout.

 

[Easy peasy]

N is the number of turns the specified volts are applied to.

 

[sabu31]

If you give me your push pull spec, ill do a transformer for you, and post it here, with all details.
..if you provide, vin, vout, pout.

The specification of the inverter are

Vin =25 V
Vout=400V
Po=500W
Fs=100Khz
Bm=0.1T
Bac=0.2T
I have used Dmax as 0.4 . Based on which I am getting turns ratio as 20. However, in simulation I see that a leakage of even 1uH at primary leads to lower boosting and requires turns ratio of around 30.

By estimating based on power ouput I am getting required core ETD44 or ETD 49.

Np=3.7
Is this value approximately correct. Does Np=4 represent one half of primary ?

--- Updated May 19, 2021 ---

N is the number of turns the specified volts are applied to.

Ok. That means its Half of the Winding right ?

 

[treez]

Hi
Have done an initial design for your transformer. As attached
It uses an ETD44/22/15
N87 material and no gap
Each primary is 5 turns of 5 strands of 7/0.28mm TEX-ELZ triple insulated wire.
Each 5 turn coil is 5 turns across the bobbin, and then terminates to the pins on the other side of the bobbin. Each one former pin terminates no more than 2 ends.
(There are 18 pins on the former, so use as many as possible without running out)
There are two of these primaries.
Then the secondary is 116 turns of two strands of 0.2mm ECW.
This is split into two 58 turn coils...which are in series with each other...and they sandwich the two secondaries which lie inbetween them on the bobbin.
The schem and LTspcie sim is as attached.
I dare say i will come back and make some adjustment due to the leakage inductance. I havent simulated leakage inductance yet, but will come back and do this.

 

[Easy peasy]

For 25V to 400V in a push pull the above turns ratio is a bit steep, one should aim for maximum utilisation at full power ( say 48% + 48% pwm )

for a 5 T pri, x 400 / 25 = 80 turns, 82T will give 410V, and taking into account the 48% D, we need 85.5T say 86 T, 25x 86/5, x 48/50 = 412.8V

so we have allowed for some losses, being 12.8V higher.

For use-able leakage at this power level, 500W, it would be adviseable to have 3 primary layers, each Bi-filar wound, with the split sec 43 + 43 Turns in between the 3 pri layers.

From dB/dt = V/(N.Ae), for ETD44, Ae = 173mm^2 so Bpk will be 73mT each way - a good choice at 100kHz

--- Updated May 20, 2021 ---

at full power there will be close to 15A rms in each pri wdg and at least 1.25A rms in the sec wdg

it would be a good idea to compute the DC winding resistance @ 100 degC for the above wdg suggestions by Treez and see what the total DC wdg losses are at full power - if they exceed 4W @ 100 degC - then it is likely the Tx will thermally run away - unless force cooled ...

--- Updated May 20, 2021 ---

the o/p choke will be 75 - 100% of the size of the Tx ...

 

[treez]

.....I agree with your Triple interleaving to reduce leakage inductance is a big improvement. For my effort of post 8, i would need a bigger former for that as my "single sandwich" had already taken up all the vertical room in the former. So i would have to move up to a ETD49 or bigger, then i could do the triple interleaving.
Each of my primary "halves" was 5 turns of 7/0.28 TEX-ELZ, which is 42 milliohms per metre. So each primary half had resitance at DC of 3.26 milliohms. This would have meant 950mW of loss if it was DC current. (total of 1.9W of loss for pri). Of course thats at 20degc, ....100degc resistance isnt quoted in datasheet.

.......So you are winding each of the primary halves with each other bi-filar?...i agree thats best, but since each are multi-strand (of TEX-ELZ) in my case, i am going to struggle for room in the former like that....i take it that you are going to be using something different than TEX-ELZ?...or a bigger former?

 

[Easy peasy]

more layers means the wires can be thinner in each layer.

--- Updated May 20, 2021 ---

100 degC is 1.3 x R @ 20 deg C

 

[treez]

Hi
Since Easy Peasy is one of the world’s best working SMPS designers, I am not going to object to his solution of post #9 above. He has most probably sucessfully produced it for several customers already.

However, I feel that the OP may like a solution using standard offtheshelf formers with standard TEX-ELZ wire, with a relatively simple winding structure. So I have now changed the transformer design to the following, to slightly reduce leakage..


Two primaries P1 and P2 (obviously, as its pushpull)
Each primary is 5 turns of 5 strands of 7/0.28 TEX-ELZ.
The single secondary coil, S, is 114 turns, but this is made up of three layers of 38 turns. These are all 7/0.15mm TEX-ELZ

So the layer stack-up, on the ETD44 bobbin is as follows…

S
P2
S
P1
S

..As you know, and you can certainly see on an LTspice simulation…the leakage inductance is going to be excessive, and will likely result in more than 30W of dissipation in a primary clamp. It won't attract praise from Greta Thunberg. Not only that, but the level of leakage inductance will mean that I will not be able to achieve Easy Peasy’s 96% duty cycle (since the primary leakage delays the rise of the primary current too much). Therefore, I have stuck with a 70% duty cycle.

What have I done with all that loss associated with the leakage inductance?.....well…..as the attached shows, I have mounted a flyback converter grounded to the 25V input….this flyback is regulated such that it prevents the primary clamp voltage going above 180V….and this flyback literally shovels the leakage inductance derived energy to the pushpull output…so its like a lossless snubber (or less-losses snubber). The LTspice sim attached shows its operation...(Unfortunately this sim takes ages to run, unless you can borrow a NASA main-frame computer, or can find one cheap on e-bay)

All the design docs are as attached.

The ETD44 former has 18 pins, and I simply cannot do any more interleaving than I already have, since I am using all the pins as it is in order to terminate the turns that I have now.

P1 alone uses 6 pins
P2 another 6 pins
The three Sec layers use the remaining 6 pins.

ETD44 former and core:
https://www.tdk-electronics.tdk.com/inf/80/db/fer/etd_44_22_15.pdf

All my layers start on one side of the bobbin, and are terminated on the other side….this means I do not overfill the bobbin, because I don’t have those dreaded “coil-ends-which-get-taken-back-across-the-former-for-termination”

--- Updated May 22, 2021 ---

For your spec, I think I would actually prefer a simpler solution involving a Pre Boost converter going up to 100V. I would then just simply use a half bridge LLC to give the isolated 400V, 500W.

For the LLC, you could use eg a power integrations HiperLLC chip, which contains the two power fets and controller and fet drives on the one chip. Theres also a similar one from Fairchild, and again from Infineon.

 

[Easy peasy]

It is a newbie oversight not to have bifilar or similar pri wdgs on a push pull - because as a mosfet turns off the energy path for that leakage is into the other pri wdg - which then acts as a clamp for Vds, not to have them interleaved introduces a lot of leakage between primaries which makes the turn off a lot more lossy - working on any push pull above a few 100 watts shows this effect to the constructor. This is why push-pulls are such a head-ache to the newbie to power electronics ...

 

[treez]

....Thanks, i agree with what you say....however...
Supposing i just go ahead and employ the winding strategy shown in post #12 anyway...
And i get a coupling factor of say 0.995, which gives me a leakage inductance related loss of some 35W.......supposing i am prepared to just put up with that...and i shovel in enough heatsinked power resistors to manage it......what's wrong with that?.....would it not give a converter with output of 400v and 500w?......and i just put up with the label of being a maker of inefficient power supplies.

(im ignoring the fact that in post #12, the leakage inductance energy is actually recycled by way of a flyback converter, usefully shovelling the energy into the output of the push pull converter........so in this case i didnt need really low leakage inductance, because the leakage L energy is recycled?)

I am coming out with this because i am hampered with a restriction to strands of TEX-ELZ wire for the primary......5 strands for each primary.....i cannot practically wind these primaries bifiar with each other, as you know, its too physically awkward to do that.
I appreciate that you yourself have access to other special materials, which you may well have developed yourself. To these, i dont have access.

 

[Easy peasy]

push-pulls are a special case, they need low leak b/n primaries and b/n pri's and sec's ....

 

[treez]

Thanks, i wont push this if OP isnt interested...but it would be interesting to know if the "pushpull with simple winding structure and flyback energy reclamation circuit" (of post #12) is workable or not. And if not, why not?

 

[sabu31]

Thankyou treez and Easy peasy for the clarifications on Pushpull converter transformer design. Could you give a reference for the design in post #12.

The primary was mentioned as 5 turns for each half winding. The secondary for each half winding should be 100 right considering 1:20 Turns ratio .

 

[treez]

The turns ratio for the pushpull in #12 is NP1 = 5, NP2 = 5 and NS = 114.
The excel doc in that post shows this.

There is only one secondary coil...because it uses a full wave rectifier output.
The secondary is made up of three series layers of 38 turns.

 

[sabu31]

The turns ratio for the pushpull in #12 is NP1 = 5, NP2 = 5 and NS = 114.
The excel doc in that post shows this.

There is only one secondary coil...because it uses a full wave rectifier output.
The secondary is made up of three series layers of 38 turns.

Thankyou treez for the reply. I was considering centre tapped secondary. I didn't clarify in my original post.
This would mean that perhaps ETD 44 will not be able to satisfy fitting all the windings in case the transformer is centre tapped in both primary and secondary.

 

[treez]

your output current is so low you wont need centre tapped sec.
The bobbin depth is 7.12mm
The total winding depth is 2 * 1.12mm + 3 * 0.718mm = 4.39mm
So there is room for a centre tapped secondary if you want.