Leakage inductance can ruin operation of a BCM flyback?.....if no RCD Clamp

[treez]

Hi,
As we all know, when doing an offline BCM Flyback, its essential that the bias coil signal which goes to the “zero-cross” detector in the BCM controller, (to sense when its time to turn the FET back on) is not soaked in noise. However, this signal is by its very nature, a very noisy signal. It is after all, a switching node. Also, any leakage inductance in the transformer will mean this signal “bouncing” around and possibly being so noisy that it ruins proper BCM operation.

As such, it is essential to have a solid RCD clamp on the primary of any BCM flyback in order to make the zero-cross signal as noise-free as possible. (to quench all the leakage inductance induced ringing).

However, if one observes page 19 of the FSCQ1565 datasheet, one notices that this BCM flyback uses no primary RCD clamp whatsoever. -And to make matters worse, it also adds a resistor of 1nF from drain to source…..almost as if inviting the node to resonate….weird.

…….However, we also notice that this schematic comprises five secondaries. Would you agree that multiple secondaries means less overall leakage inductance, since all the leakage inductances are effectively in parallel with each other?

As such, the schem on page 19 is workable, (even though it has no primary RCD clamp) because the leakage inductance, and hence the “leakage inductance induced ringing”, is much less of a problem?

FSCQ1565 datasheet (BCM flyback controller)

https://www.onsemi.com/pdf/datasheet/fscq1565rt-d.pdf

 

[scopeprobe]

1. The ZCD is designed to monitor the choke voltage collapsing, You can put a small RC filter on it just to limit high frequency noise effecting the zero crossing.

2. Its not 'essential' to have a RCD clamp, in some cases its actually favourable not to as RCD snubbers can create EMI due to inherent harmonics. As the natural ring frequency of the parasitics around the switching node is low in harmonics you can sometimes just overrate the switch voltage (they have a 650V Mosfet) or use a low leakage transformer design to give a smaller spike - The energy will just go to the load

3. A simple capacitor across the switch MOSFET may just be to reduce the frequency of the Ring such that its signature is outside the EMI measurement window.

4. They use capacitors around the diodes in a similar manner, this will change the frequency of any ringing and the ESR will provide some loss.

5. Its notable that their schematic on Page 19 makes no provision for EMI on any of their secondaries so will be a potential EMI problem if any of those lines happen to come off the board out of a box. If you were to copy the design you would potentially need to consider this and whether there will be additional filtering requirements needed

5. Line regulation of the outputs will be poor without a good transformer layout. Only the 24V and 125V look to have any form of regulation

 

[treez]

As the natural ring frequency of the parasitics around the switching node is low in harmonics you can sometimes just overrate the switch voltage (they have a 650V Mosfet) or use a low leakage transformer design to give a smaller spike - The energy will just go to the load

Thanks, i know what you mean by this...you are saying that energy goes to the load. Because as i am sure you well know, energy in the leakage inductance does not end up going to the load. As you know, if we have no RCD clamp, then the leakage inductance energy ends up getting burned up in the PCB traces and in the "skin" of the "skin effected" primary which has high resistance to the high frequency ringing.

Its not 'essential' to have a RCD clamp, in some cases its actually favourable not to as RCD snubbers can create EMI due to inherent harmonics. As the natural ring frequency of the parasitics around the switching node is low in harmonics you can sometimes just overrate the switch voltage

Thanks, i have heard other engineers saying this. As much as i kind of am attached to it as an idea, and find it appealing, IMHO i dont readily believe in this. I think the "natural" ring, (without an RCD clamp) ..though it appears to be a fairly nice sinusoid, i believe that the parasitic capacitances involved change their value as the voltage on them changes throughout the ring, and so the ring is actually not that sinusoidal after all.....and its also of a relatively high amplitude, because of it not being clamped, so in the end, this not-so-sinusoidal ring has a lot of higher harmonics in it which cause more EMC problems than when having an RCD clamp across the primary. Or so i postulate. I stand ready to be zapped wrong on this one. However, maybe it just a different spectrum of EMC problems that you get with either way. I think the worst thing about having no RCD clamp, i am sure you would agree, is the problem of high primary overcurrents putting much energy into the leakage, which then goes on to overvoltage the fet...eg a full load to no load transient, or a non-soft-start or a non-soft-restart...etc etc

 

[scopeprobe]

Thanks, i know what you mean by this...you are saying that energy goes to the load. Because as i am sure you well know, energy in the leakage inductance does not end up going to the load. As you know, if we have no RCD clamp, then the leakage inductance energy ends up getting burned up in the PCB traces and in the "skin" of the "skin effected" primary which has high resistance to the high frequency ringing.

I will try and rephrase.

If the leakage spike isn't causing a problem for the Mosfet Peak Voltage or Conducted Emissions then it is not essential to have a RCD Clamp to disipate the energy (this will unecessarily effect your efficiency).

The leakage spike would still be there but as relatively pure ring and the energy would just disipate. Some into the input filter, some into the output filter, some into the output load and some as radiated emissions off the transformer to name a few.

Transformer design & Power Levels is everything of course.

Transformers have interwinding capacitance so by load i mean the energy will disipate in its lowest impedance paths.

--- Updated Apr 6, 2021 ---

Thanks, i have heard other engineers saying this. As much as i kind of am attached to it as an idea, and find it appealing, IMHO i dont readily believe in this. I think the "natural" ring, (without an RCD clamp) ..though it appears to be a fairly nice sinusoid, i believe that the parasitic capacitances involved change their value as the voltage on them changes throughout the ring, and so the ring is actually not that sinusoidal after all.....and its also of a relatively high amplitude, because of it not being clamped, so in the end, this not-so-sinusoidal ring has a lot of higher harmonics in it which cause more EMC problems than when having an RCD clamp across the primary. Or so i postulate. I stand ready to be zapped wrong on this one. However, maybe it just a different spectrum of EMC problems that you get with either way. I think the worst thing about having no RCD clamp, i am sure you would agree, is the problem of high primary overcurrents putting much energy into the leakage, which then goes on to overvoltage the fet...eg a full load to no load transient, or a non-soft-start or a non-soft-restart...etc etc

Amplitude is the problem, to control amplitude you have to design the windings to be low leakage and if thats not possible then your either looking at damping (efficiency loss) as you already suggested or alternative topologies with better capability.

The frequency of the ring won't really change much with voltage. The only thing that really changes is the peak current going through the transformer which would typically be tracking the haversine. The peak current will be at the peak of the low line voltage so should be when the leakage spike is at its largest. From a mosfet perspective high line is more the problem to prevent avalanche of the mosfet.

Flybacks arn't great for EMI anyway due to the large switching currents, i 100% agree on this. I typically discount them above 50W and move towards interleaved or even the forward converter topology which allow for continous mode operation which allow methods to eliminate leakage by putting the energy back into the line.

 

[treez]

The frequency of the ring won't really change much with voltage.

Thanks, i am sure you would agree that when the FET switches off, (assume no RCD clamp here), the drain voltage will ring up, and as it gets higher, the Cds capacitance will get smaller. As such, the sinusoid will not be a pure sine, because the LC thats ringing is actually changing as the Vds changes. As you know, FET junction capacitances change as the voltage across them changes. As such, we dont get a pure sinusoid ring. Its got harmonics in it, due to it being a distorted sine.

Would you agree with the point in the top post that having fives secondaries gives a relatively low leakage inductance as seen from the primary?

 

[scopeprobe]

Thanks, i am sure you would agree that when the FET switches off, (assume no RCD clamp here), the drain voltage will ring up, and as it gets higher, the Cds capacitance will get smaller. As such, the sinusoid will not be a pure sine, because the LC thats ringing is actually changing as the Vds changes. As you know, FET junction capacitances change as the voltage across them changes. As such, we dont get a pure sinusoid ring. Its got harmonics in it, due to it being a distorted sine.

Would you agree with the point in the top post that having fives secondaries gives a relatively low leakage inductance as seen from the primary?

For the leakage inductance and Cds i would normally assume for them to remain fairly consistant and that they don't tend to move around. The leakage ring is normally pure. Yes, device characteristics can change slightly but not significantly enough to worry about.

I purposely didn't answer the question regarding the secondaries as thats not really my Forte. My knowledge of windings is that everything is a trade off and good primary to secondary coupling is what reduces leakage inductance. Based on this i would have said more windings would make coupling worse and therefore increase leakage inductance but i'm sure therer are people with more expertise on this to give a more assured response.

 

[treez]

Theres pg 10 of this...

https://www.infineon.com/dgdl/SPP_I_A11N60C3_E8185_Rev[1].3.1.pdf?folderId=db3a3043163797a6011638933eda014b&fileId=db3a3043163797a6011638a2fdee01a3

...which shows Cds (Coss) at 600V as 35pF......and then its 48pF at 200V

This shows drain voltage ringing when no RCD clamp used and using 128W offline flyback
**broken link removed**

...as you can see, there is a big voltage variation on the ringy drain.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

All the design examples of "no_RCD_clamp" 100W+ Offline BCM flybacks with the FSCQ1565 BCM Flyback controller have secondaries with low currents (<1A).

This , i feel certain, is a pre-requisite for a 100W+ Offline flyback that has no primary side RCD clamp. Because with eg a 24V, 5A Offline BCM flyback with no primary RCD clamp, ...and you end up with primary and secondary currents like this...
(although the LTspice sim isnt simulating the skin effect here so not quite as bad as this)

Here is 120W Offline flyback pri and sec currents with NO RCD clamp on pri....(5A output)
**broken link removed**

Here is 120W Offline flyback pri and sec currents with RCD clamp on pri.... (5A output)

Flyback-Pri-and-sec-currents-with-RCD-clamp hosted at ImgBB

Image Flyback-Pri-and-sec-currents-with-RCD-clamp hosted in ImgBB

ibb.co

So do you agree really that with >1A secondary current, you really should be using an RCD clamp in an offline BCM flyback?....otherwise the ringing peaks in the current are excessive (as above) , you agree?

FSCQ1565 datasheet

https://www.onsemi.com/pdf/datasheet/fscq1565rt-d.pdf

AN4146 app note

https://s1.dtsheet.com/store/data/000036560.pdf?key=996e2cd0cec9d0bfbeaabf3e495b7c80&r=1

 

[scopeprobe]

Thats a delta of 13pf, the effect of that will be negligible compared to the general tolerances of the transformer and its associated leakage inductance which will likely be in the uH.

Based on you first simulation your spike is approx 750V. If you are fixed with the transformer design try considering a controller that allows the use or contains a 900V switch. Assuming the frequency is not a problem for EMI wheres the problem? The energy is going to the load so you have good efficiency.

The damping will help if EMI is an issue but you burn a few watts in the supply killing your efficiency and giving yourself a thermal issue so as i said in one of my previous messages before looking to snubbers (that will cause thermal challenges) you should focus on getting a good transformer design to minimise the leakage spike or even consider a more appropriate topology if it is of significant concern.

Of course there is a use for damping but good consideration of the task up front will give you less issues later.

 

[Easy peasy]

haven't read all the posts - but yes - leakage is critical to flybacks of any type above about 50W, for our 200W versions the leakage is < 500nH

for good reason. To blunt the effect of the leakage spike you really have to snubber or catch the energy on a cap and then bleed it back to the pri ( or converter to the sec side ). For our very quiet ( RFI) flybacks we have snubbers every-where, across the fet, Tx, RCD catch diode, Tx sec side - sec side diode. ( and low leakage to keep the total snubber power down )

 

[treez]

To blunt the effect of the leakage spike you really have to snubber or catch the energy on a cap and then bleed it back to the pri

Yes that sounds good, but i believe we are all in agreement, that if no RCD clamp is used, (and no regenerative snubber) then the energy in the leakage inductance does *not* end up going to the load. The 0.5*L*i^2 energy does not go to the load, but just gets burned up in the (outer portion) of the primary winding resistance, etc (skin effect)

 

[mtwieg]

There are numerous ways to deal with leakage inductance, but none of them are mandatory in general. The various methods address different side effects of leakage inductance, such as EMC, component dissipation, device breakdown, etc.
For example, a simple RC snubber will reduce voltage stress, and tend to reduce EMC and FET dissipation. It's the most general-purpose method.
The clamp-type RCD snubber is mainly intended to limit peak voltage stress. It also can affect EMC and efficiency, for better or worse.
A slew-limiting RCD snubber is mainly intended to reduce dissipation in the FET, but will also tend to reduce voltage stress and EMC. Though in my experience, slew-limiting snubbers will degrade overall efficiency more than other snubbers.

Which type and how many are used is always application specific.

 

[Easy peasy]

If you have an RCD snubber with the cap going to gnd - then the bleed resistor can return half of the energy back to the input - but the cap needs to be higher voltage ...

--- Updated Apr 25, 2021 ---

@ MTWeig, "a simple RC snubber will reduce voltage stress, and tend to reduce EMC and FET dissipation."

unfortunately for the mosfet, for a simple RC snubber the mosfet gets an extra "hit" at turn on as it charges the simple RC snubber ...! very good for removing turn off losses though ...

--- Updated Apr 25, 2021 ---

if no RCD clamp is used, (and no regenerative snubber) then the energy in the leakage inductance does *not* end up going to the load. The 0.5*L*i^2 energy does not go to the load, but just gets burned up in the (outer portion) of the primary winding resistance, etc (skin effect)

Mmm - for a fet with no clamp - the leakage energy goes into the fet at avalanche,

put a cap across the mosfet - and that energy will eventually return to the input - if you wait for the ringing to die down

 

[treez]

Thanks, but in a flyback converter, i am sure you would agree, putting a cap across the fet does not result in the energy in that cap going back to the input...it gets wastefully discharged by the fet, when the fet turns on.

To put leakage energy back to the input...only a two switch flyback or forward can do that....not single switch flyback.

 

[Easy peasy]

aah no - not for a QR flyback .... which is why they are so good ...

 

[treez]

Thanks, but are we talking about the same thing here? I am stating that unless a single switch flyback has some regenerative snubber arrangement, then the energy in the leakage inductance is wastefully dissipated in the primary winding and circuit trace resistances. Especially so since the leakage ring is a few MHz usually and the skin depth at 1MHz is just 6um. None of the energy in the leakage inductance ends up getting recycled back to the input capacitor. None of the energy in the leakage inductance gets sent to the load. It is all wastefully dissipated. Would you agree?
The attached LTspice sim demo's this. Also a PDF schem is also attached.

In the simulation you can clearly see that there is no path via which the leakage energy can get back to the input capacitor.

 

[mtwieg]

@ MTWeig, "a simple RC snubber will reduce voltage stress, and tend to reduce EMC and FET dissipation."

unfortunately for the mosfet, for a simple RC snubber the mosfet gets an extra "hit" at turn on as it charges the simple RC snubber ...! very good for removing turn off losses though ...

Right, in some cases the RC snubber can increase turn-on losses more than it decreases turn-off losses. Depends on the relative contribution of Coss and Vds*Ids overlap to switching losses. At max load, overlap losses will usually dominate, and thus the snubber should slightly reduce dissipation.

 

[Easy peasy]

then the energy in the leakage inductance is wastefully dissipated in the primary winding and circuit trace resistances.

for a simple flyback the energy is largely absorbed by the RCD snubber - in the R, for no snubber the energy goes into the wdg cap and the fet cap - if the fet avalanches then some energy goes there - if it does not then when the fet is off the high voltage on its drain will go thru the Tx pri and back to the source.

for VHF ringing seen on an RCD snubber at the instant of turn off - yes this is dissipated in a variety of ways - some of it RFI - some of it damped by wdg R - this is not the totality of the energy in the primary's share of the leakage inductance however - it is but a fraction.

For a good QR flyback - with no RCD or other snubber - almost all the energy in the leakage L goes back to the source - which is why it is a good choice.

--- Updated Apr 26, 2021 ---

the ratio of extra turn on losses to reduced turn off losses in direct proportion to how fast you turn the fet off.

the extra losses due to turn on are 0.5 C V^2 Freq, if you turn on too slowly you get extra overlap losses - there is always a sweet spot trade off for turn on time and RFI created from too fast a turn on vs extra heat in the sink for too slow.

For improperly snubbered if the turn off is too fast / aggressive - then there may well be voltage overshoot on the mosfet - this can be cured by a bigger snubber with the right RC combination - or by turning off more slowly ( extra heat in the sink ) - these are common trade offs for the power electronics designer.

 

[Easy peasy]

As we all know, when doing an offline BCM Flyback, its essential that the bias coil signal which goes to the “zero-cross” detector in the BCM controller, (to sense when its time to turn the FET back on) is not soaked in noise. However, this signal is by its very nature, a very noisy signal. It is after all, a switching node. Also, any leakage inductance in the transformer will mean this signal “bouncing” around and possibly being so noisy that it ruins proper BCM operation.

- just referring to your actual question posted - the zero cross ( falling Vds ) is well after the noise generated at initial switch off - and after all the energy is exhausted from the Tx gap to the secondary, only then does the Vds start to ring down, etc ... so your question is moot - there is no correlation.

 

[Easy peasy]

there is one point that needs just a bit more clarification - if the energy in the leakage is say 0.5 x 1.5uH x 4A^2 = 12uJ say,

and you have a 1n5 cap across the transformer - then one might assume this cap will ring up to ( 0.5 C V^2 ) = 126 Vpk - if the supply rail is 300V you would then get 426 Vpk **

note we assume all the leakage energy is now in this cap ( assuming a fast turn off of the main fet - gate drive goes to zero in < 40nS )

thus if the flyback volts ( i.e. the re-flected o /p volts are 120V or so ) then the "overshoot" "would" be minimal - if the sec side could pick up the current more or less instantaneously - but it can't - why .. ? because the leakage is split - pri & sec - ** see below

let us assume a 300V wdg on the pri side and a 24V wdg on the sec side, with the turns such that 25Vout ( diode ) = 120V reflected ( flyback volts )

for 4A pk in the pri - this will be 120 / 25 x 4 = 19.2 A pk initially in the sec wdg

But for 1.5uH Llk on the pri we must have 1.5uH x 25^2 / 120^2 = 65nH on the sec side of leakage - this doesn't seem like much - but ...

from V / L = di /dt we now see that it will take dt = di x L / V = 250nS for the sec current to go from 0 - 19.2 amps with a drive of 5V, i.e. if the o/p cap is sitting at 24VDC, the internal EMF seen by the sec wdg must go up to 24 + 1 + 5V = 30V, this is 144V on the pri side

So - if we clamp or limit the pri side flyback volts to 144V, it will take 250nS for the current to swap over to the sec side, and if we want half this time we need 288V of flyback approx ( and ~ 60V of internal EMF applied to the sec wdg ) [ N.B. this is 144V x 2A ave x 250nS x Freq, of losses, at 100kHz = 7.2 watt ]

This is why lowering the leakage on a flyback is such a good thing to do - esp at high freq - as the commutation time of the current goes down and the time the clamp spends at the needed flyback voltage is reduced.

** here is the below: For the resonant cap approach mentioned above - we have assumed an instantaneous pickup of the current on the sec side - which we have just seen don't happen due to the sec side leakage - what does happen ?

Remember there is a lot of energy stored in the air gap - the terminal volts of the transformer are not happy ( at mosfet turn off ) until all that current is going somewhere - initially it charges our resonant cap - but it cannot flow in the sec side until the terminal volts on that side exceed Vo + Vdiode - and then by some margin to speed up the transfer ( as we saw above ).

So for our 1.5nF cap we now assume it will charge at 4A to 0A over 250nS ( approximately ) this is ( i / C = dV /dT ) = 333 volts pk - straight away we feel intuitively this can't be quite right - indeed because as the flyback volts increase - the rate of current pick up in the sec increases too - it is a quadratic equation that needs solving,

and there is step change at the beginning as no current will flow to the sec until we get at least 120V of flyback volts on the pri,

so the cap charges at near 4A until we get to 120V and then the charging current reduces as the current is picked up on the sec side, i/c = dV /dT = 45nS to get to 120V,

if we assume the flyback volts then go from 120 - 220V the average overdrive on the sec is 50V x 25 / 120 = 10.4V, and therefore the commutation time will be V/L = di/dt, = 120nS ( + the 45nS needed to get to 120V on the pri ) - [ actually slightly longer as we have not allowed for the sec diode drop.]

So even the simple flyback is a complicated wee beastie when you get into the detail of turn off - and how to calc a capacitor only snubber for a given leakage and a given Ipk and a given turns ratio ( we have assumed 1.5nF across the Tx, but it can be just across the fet ( smaller C ) or a combination.

The analysis is still not quite accurate - as - there is a resonant action between the pri side leakage and the cap, and as the current in the pri side leakage reduces - the voltage on the cap curves over as the top of a sinusoid - reaching a peak as the current in Lk pri falls to zero - the result of this is that the peak V will be a teeny bit lower and the commutation time will be a teeny bit shorter [ as the volt-seconds are greater with the sine wave rather than a linear approximation.]

Then we will have a ring as the peak flyback volts are higher than the reflected o/p volts - as this voltage settles to the correct one ( 120V in this case ) the extra energy in the 1.5nF will go to the o/p - if connected across the Tx only, or to the o/p and i/p if it is connected across the fet.

This is why an accurate spice model is such a great tool for designing flybacks - and their snubbers - if you set intelligent values for the leakages.

 

[mtwieg]

because the leakage is split - pri & sec - ** see below

I think your analysis is not wrong, but be aware that it's really easy to misinterpret your model of the transformer once you introduce two separate leakage inductances.

One of the issues with transformer modelling (here we'll assume it's just a pair of coupled inductors, no nonlinearities or capacitances) is that there's basically an infinite number equivalent circuit models for it. The model need only be defined by three parameters; for example LTspice uses the two open circuit inductances and the coupling factor. Inside that black box you can draw a model which has leakage inductance one side or both. But that's basically just an academic exercise. The actual behavior at the ports won't care, what matters is that the model is accurate.

So it's not necessary to have a model with both primary and secondary inductances (LLp=Lp*(1-k) and LLs=Ls*(1-k), respectively). We can equivalently use LLp=Lp*(1-k^2) and LLs=0. But it's definitely incorrect to only consider a primary side leakage with value LLp=Lp*(1-k).