FlyingDutch
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Hello,
I am trying to implement SRAM controller (on external PCB with CY7C1041DV33 SRAM IC) connected to QMTECH Spartan7 board. Here is link to Spartan7 board:
https://pl.aliexpress.com/item/32959887279.html?spm=a2g17.12010612.8148356.4.1a4954bdnHb81i
The PCB board and other details I described in this post:
https://www.edaboard.com/threads/static-ram-ic-selection-for-full-hd-resolution-frame-buffer.395013/
The project is written in VHDL and is based on this Github project (for Altera DE1 FPGA board)
https://github.com/chkrr00k/sram-controller
I modified it a bit - here are sources in VZHDL:
"sramTest.vhd"
"test.vhd"
"sram.vhd"
Sorry i wasn't able to fit all in one message - here is continuation:
And here is constraint file "sramTest.xdc" for that FPGA boasrd with Spartan7:
I have warnings in implementation phase that SRAM_DQ (inout) bus hasd no proper input and output buffer. Here is this warniing:
I tried to put IOBUF for port SRAM_DQ using as atributes in VHDL code or XDC file but they are ignored.
Could somebody to help me put IOBUF for SRAM_DQ port?
Thanks in advance anr Regards
I am trying to implement SRAM controller (on external PCB with CY7C1041DV33 SRAM IC) connected to QMTECH Spartan7 board. Here is link to Spartan7 board:
https://pl.aliexpress.com/item/32959887279.html?spm=a2g17.12010612.8148356.4.1a4954bdnHb81i
The PCB board and other details I described in this post:
https://www.edaboard.com/threads/static-ram-ic-selection-for-full-hd-resolution-frame-buffer.395013/
The project is written in VHDL and is based on this Github project (for Altera DE1 FPGA board)
https://github.com/chkrr00k/sram-controller
I modified it a bit - here are sources in VZHDL:
"sramTest.vhd"
Code:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.all;
entity sramTest is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic;
RESET_N : in std_logic;
LEDR : out std_logic;
LEDG : out std_logic;
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_CE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_WE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic
);
end;
architecture RTL of sramTest is
signal clock : std_logic;
signal clockVGA : std_logic;
--signal RESET_N : std_logic;
signal data : std_logic_vector(7 downto 0);
signal addr : std_logic_vector(17 downto 0);
signal i : std_logic_vector(15 downto 0);
signal o : std_logic_vector(15 downto 0);
signal w : std_logic;
begin
test : entity work.test
port map(
CLOCK => clock,
RESET_N => RESET_N,
LEDG => LEDG,
LEDR => LEDR,
KEY => KEY,
DATA => data,
I => i,
O => o,
ADDR => addr,
W => w
);
sram : entity work.sram
port map(
CLOCK => clock,
RESET_N => RESET_N,
ACTION => w,
DATA_OUT => o,
DATA_IN => i,
ADDR => addr,
SRAM_ADDR => SRAM_ADDR,
SRAM_DQ => SRAM_DQ,
SRAM_CE_N => SRAM_CE_N,
SRAM_OE_N => SRAM_OE_N,
SRAM_WE_N => SRAM_WE_N,
SRAM_UB_N => SRAM_UB_N,
SRAM_LB_N => SRAM_LB_N
);
end architecture;"test.vhd"
Code:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.all;
entity test is
port (
CLOCK : in std_logic; -- clock in
RESET_N : in std_logic; -- reset async
LEDG : out std_logic;
LEDR : out std_logic;
KEY : in std_logic;
DATA : in std_logic_vector(7 downto 0);
I : out std_logic_vector(15 downto 0);
O : in std_logic_vector(15 downto 0);
W : out std_logic;
ADDR : out std_logic_vector(17 downto 0)
);
end entity;
architecture behav of test is
signal S_HC : integer range 0 to 9;
signal S_LC : integer range 0 to 9;
signal i_value : integer range 0 to 99;
signal S_READ : std_logic_vector(15 downto 0);
begin
Test : process(CLOCK, RESET_N)
begin
if rising_edge(CLOCK) then
LEDG <= '0';
LEDR <= '0';
if KEY = '0' then
ADDR <= "000000000000000000";
I <= "00000000" & DATA;
W <= '1';
LEDG <= '1';
elsif KEY = '0' then
ADDR <= "000000000000000000";
S_READ <= O;
W <= '0';
LEDR <= '1';
end if;
end if;
end process;
end architecture;"sram.vhd"
Code:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.all;
entity sram is
port (
CLOCK : in std_logic; -- clock in
RESET_N : in std_logic; -- reset async
DATA_IN : in std_logic_vector(15 downto 0); -- data in
DATA_OUT : out std_logic_vector(15 downto 0); -- data out
ADDR : in std_logic_vector(17 downto 0); -- address in
ACTION : in std_logic; -- operation to perform
SRAM_ADDR : out std_logic_vector(17 downto 0); -- address out
SRAM_DQ : inout std_logic_vector(15 downto 0); -- data in/out
SRAM_CE_N : out std_logic; -- chip select
SRAM_OE_N : out std_logic; -- output enable
SRAM_WE_N : out std_logic; -- write enable
SRAM_UB_N : out std_logic; -- upper byte mask
SRAM_LB_N : out std_logic -- lower byte mask
);
end entity;
architecture behav of sram is
-- ram fsm
type RAM_FSM_T is (
OFF_F,
READ_F,
WRITE_F
);
signal S_RAM_STATE : RAM_FSM_T := OFF_F;
-- controller state;
signal S_ACTION : std_logic; -- [0 - read] [1 - write]
signal S_READ : std_logic_vector(15 downto 0);
begin
RamController : process(CLOCK,RESET_N)
begin
if(RESET_N = '1') then -- async reset
S_READ <= "0000000000000000"; -- reset the data read signal
SRAM_CE_N<='0'; -- enables the chip (all the time?)
SRAM_LB_N<='1'; -- mask low byte
SRAM_UB_N<='1'; -- mask high byte
SRAM_ADDR <= (others => '-'); -- set the address as "don't care" (must preserve low the bus)
SRAM_DQ <= (others => 'Z'); -- set the data bus as high impedance (tristate)
elsif rising_edge(CLOCK) then -- high clock state (do something!)
SRAM_ADDR <= (others => '-'); -- "don't care"
SRAM_DQ <= (others => 'Z'); -- high impedance
if ACTION = '0' then -- READ
S_ACTION <= '0'; -- tells the fsm to read
SRAM_ADDR <= ADDR; -- notify the address
SRAM_LB_N <='0'; -- unmask low byte
SRAM_UB_N <='0'; -- unmask high byte
DATA_OUT <= SRAM_DQ(15 downto 0); -- read the data
elsif ACTION = '1' then -- WRITE
S_ACTION <= '1'; -- tells the fsm to write
SRAM_ADDR <= ADDR; -- notify the address
SRAM_LB_N <= '0'; -- unmask low byte
SRAM_UB_N <= '0'; -- unmask high byte
SRAM_DQ <= DATA_IN; -- send the data
end if;
end if;
end process;
FSM : process(S_ACTION)
begin
SRAM_OE_N <= '1'; -- output disabled
SRAM_WE_N <= '1'; -- write disabled
if(S_ACTION = '0') then
--read
S_RAM_STATE <= READ_F;
SRAM_OE_N <= '0';
else
--write
S_RAM_STATE <= WRITE_F;
SRAM_WE_N <= '0';
end if;
end process;
end architecture;
--- Updated ---
Sorry i wasn't able to fit all in one message - here is continuation:
And here is constraint file "sramTest.xdc" for that FPGA boasrd with Spartan7:
Code:
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
#############SPI Configurate Setting##################
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
############## clock and reset define##################
create_clock -period 20.000 -waveform {0.000 5.000} [get_ports CLOCK_50]
set_property PACKAGE_PIN H11 [get_ports CLOCK_50]
set_property IOSTANDARD LVCMOS33 [get_ports CLOCK_50]
###set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {CLK50MHz_IBUF}]
#Keys
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports RESET_N]
set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports KEY]
#LEDs
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports LEDR]
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports LEDG]
#SRAM_ADDR
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {SRAM_ADDR[17]}]
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {SRAM_ADDR[16]}]
......... shortened
#SRAM_DQ
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {SRAM_DQ[15]}]
#set_property IOB TRUE [get_ports {SRAM_DQ[15]}]
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {SRAM_DQ[14]}]
#set_property IOB TRUE [get_ports {SRAM_DQ[14]}]
.... shortened
set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {SRAM_DQ[1]}]
set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS33} [get_ports {SRAM_DQ[0]}]
#sYGNALY STERUJACE sram ic
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports SRAM_CE_N]
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports SRAM_OE_N]
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports SRAM_WE_N]
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports SRAM_UB_N]
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports SRAM_LB_N]I have warnings in implementation phase that SRAM_DQ (inout) bus hasd no proper input and output buffer. Here is this warniing:
Code:
DRCNetlistPortRequired Buffer[DRC RPBF-3] IO port buffering is incomplete: Device port SRAM_DQ[0] expects both input and output buffering but the buffers are incomplete.
--- Updated ---
I tried to put IOBUF for port SRAM_DQ using as atributes in VHDL code or XDC file but they are ignored.
Could somebody to help me put IOBUF for SRAM_DQ port?
Thanks in advance anr Regards
Last edited:
