Biasing transimpedance OPAMP amplifer

[yefj]

Hello , I have a 60 dB voltage amplifier,where each input has a Vdc source which keeps its bias point.
I need to convert it into a current amplifier as shown bellow
how do i BIAS my opamp when i use a current source input?
Thanks.

 

[KlausST]

Hi,

It depends on your power supply and Opamp type. Sadly not shown.

Klaus

 

[yefj]

Hello , a schemtics of my two stage opamp voltage amplifier.
I have tried to implement the feedback loop as shown bellow,but again i am not sure about the BIAS point part with the current source.
Another thing is that the feedback affect the bias point.
What should i do with BIASING in this case?
Thanks.

OPAMP only

OPAMP with feedback

Hi,

It depends on your power supply and Opamp type. Sadly not shown.

Klaus

 

[Ata_sa16]

Your opamp is NMOS input it means that you need a DC bias at input equal to VDS(NMOS) + VDS(NMOS) which is equal to 2*Vov + vth

In your loop the positive node must be connected to DC bias.

 

[sutapanaki]

Your first picture doesn't make much sense. You can't test the amplifier by just connecting two (equal perhaps) voltage sources to the inputs. You need to have at least a DC feedback around the amplifier to keep the operating point stable.
The current input together with the feedback resistor should work, it is not much different than the normal inverting configuration opamp with negative feedback. But you need to make sure that Vdd-Iin*Rfb >= Vdsat where the Vdsat is the overdrive voltage of you output stage PMOS (given the direction of the input current).

 

[yefj]

THe first picture has equal Vdc but on one source i pult 1Vac for Gain testing.
"Your first picture doesn't make much sense. You can't test the amplifier by just connecting two (equal perhaps) voltage sources to the inputs."

So you suggest me to connect VDD BIAS in series with the current source(connecting to the gate of the input)?
I have been tought that no DC voltage drop should be allowed on the feedback loop.

"But you need to make sure that Vdd-Iin*Rfb >= Vdsat where the Vdsat is the overdrive voltage of you output stage PMOS (given the direction of the input current)."

- - - Updated - - -

Could someone draw a diargram of the biasing part of this circuit so i can see how we keep the BIAS point correctly.

 

[sutapanaki]

Putting a 1V ac source doesn't do anything to the DC operating point. It is there only for ac simulation and the simulator ignores it when finding the OP.

No, I don't suggest connecting anything in series with the current source. What you should do is something like this: connect the output to the gate of MN2 of the differential pair. You can leave in the feedback the resistor or just short the output to the input. Run DC operating point simulation. In this setup, if you have enough gain and good OP for the transistors, the two inputs should be at about the same voltage and since the output is also connected to the input, the output should be at that same voltage.
Then, you can keep this configuration and connect an ac current source the way you showed in your second picture and run ac analysis to check the trans-resistance gain in frequency.
You should also run loop gain analysis to check for the stability of the loop.
And after you are done with all this, you can go run transient analysis.

 

[DesignSpace]

1. You are designing a Transimpedance Amplifier (including Rf), which by nature has a low input impedance. Rin_of_TA = is quite low because of the feedback connection : Shunt - Shunt.

2. Because of this, its input voltage bias point is already set and that is going to be whatever you apply to the positive input terminal of the opamp Vin+ = Vin-

3. Now to your question regarding the dc bias voltage of the current source... This isn't the question you should be asking, because in an ideal scenario it doesnt really matter... Let me try to explain:

Remember the TA's input is a low impedance node. You are going to drive the TA with a proper Current Source, which by nature has a high output impedance, for example idc in analogLib. When connecting a high impedance node to a low impedance node, the existing voltage of the low impedance node always dominates. This is the bias point of the TA's input and it is already set, as mentioned above in (2). So go ahead and connect an idc to the TA referenced to ground, VDD, 1000volts, whatever you want, it doesn't matter... Personally I would connect the other side of idc to Vin+ = VDD/2 just to make everything nice and symmetrical but it really doesn't matter.

4. The question you should be asking yourself is this: in the real world, outside of cadence virtuoso, what is your Current Source going to be? And what is its allowable output voltage range going to be? If its output voltage range can handle the possible input bias points of the TA then you're fine.

5. To understand this even better you can make your own Current Source: Design a simple single stage nmos Common Source (CS) amplifier with a pmos transistor current source on top biasing it (this is basically the second stage of your opamp). Bias it properly so that its output voltage Vout sits around VDD/2. It doesnt have to be perfect just close to VDD/2 so that is works properly. This doesn't need any feedback, this is a single transistor amplifier and operates in open loop. Its output impedance is going to be rdsnmos // rdspmos and this is a relatively high impedance. This is now going to be your new Current Source in place of idc! Now connect it to the TA and see what happens... hope these tips help!

 

[Ata_sa16]

you DONT need dc for input current.

 

[yefj]

Hello, I have connected the circuit as you said
Negative input 1A AC current source
Positive input 0.8V DC voltage source
It showed me both on the NEGATIVE 0.8V and on OUTPUT 0.8V (as shown bellow)
i could understand why V_in_plus=V_in_minus=0.8V
if A=60dB and (Vin_plus-Vin_minus)*A=Vout => Vin_plus-Vin_minus=Vout/A => Vin_plus-Vin_minus=0 =>Vin_plus=Vin_minus

But why Vin_plus=Vout?
we have a resistor between then how exactly Vout gets the exact voltage of the Vin_plus?

 

[Ata_sa16]

I would suggest to make a single input opamp. That makes your work easier.
Honestly i have not seen this kind of configuration for TIA. Its whether differential input different output or single to single

Check this

https://www.ece.tamu.edu/~spalermo/ecen689_oi/lecture5_ee689_tias.pdf

So many TIA topologies

 

[yefj]

Hello, I have connected the circuit as you said
Negative input 1A AC current source
Positive input 0.8V DC voltage source
It showed me both on the NEGATIVE 0.8V and on OUTPUT 0.8V (as shown bellow)
i could understand why V_in_plus=V_in_minus=0.8V
if A=60dB and (Vin_plus-Vin_minus)*A=Vout => Vin_plus-Vin_minus=Vout/A => Vin_plus-Vin_minus=0 =>Vin_plus=Vin_minus

But why Vin_plus=Vout?
we have a resistor between then ,How exactly Vout gets the exact voltage of the Vin_plus?

 

[Ata_sa16]

There is no DC current through resistor so V- = Vout


I still believe that this topology is wrong. Try to change it. I sent you a great document.

 

[yefj]

Hello, Why there is no current threw the feedback,i could design the open loop ouput to be 0.9V DC
and input V_input_PLUS=0.8V then there could be a voltage drop and a current on the feedback loop.
Why by connectig the feedback ressistor it eliminates any voltage drop on it?
Thanks.

"I still believe that this topology is wrong. Try to change it. I sent you a great document."
Yes i am learning this document .

 

[Ata_sa16]

There is NO current flowing through Rf. It is connected to opamp V- which has 0 current and conneted to Iac which has 0 dc.
So current has no where to go ! other side of RF is like open

Do you know opamp inputs do not sink/source any current ?

 

[yefj]

Yes i understand the logic, because our source is pure AC and from the gate we cant get any DC current flowing then the current is zero
Thank you very much.

 

[DesignSpace]

Vin+ = Vin- = Vout (When no input signal is applied!) Thats correct! Thats how its supposed to work! This always holds for every opamp circuit in negative feedback and thats the reason why we choose Vin+ to be Vdd/2 specifically, so that the opamp's output sits half way between the supply rails, allowing it this way to have the maximum possible swing when it has to go up and down (when signal is applied) ! : )

Even though you designed it to sit around 0.9V in Open Loop Operation, when you apply negative feedback that is going to change! The negative feedback connection is going to determine what the output's voltage level is going to be and that is going to equal the voltage at Vin+.

By the way, what kind of technology process are you using?

 

[sutapanaki]

As I said in my previous post, when you connect an AC input current source it is ignored for DC simulation. It is only valid when you do ac simulations. So, the current source is not there when you only check the operating point. Did you check your loop stability?