DC operating output voltages of the Fully differential amplifier is not equal

[Junus2012]

Hello,

The post layout output voltages vo+ and vo- of the fully differential amplifier is not equal under DC operating point . Ideally, they must be equal and both equal to VCM. In my case they are not equal but thier average is equal to VCM.

Does this explain the offset voltage ? how can I compensate for the offset voltage of the fully differential amplifier ?

Thank you

 

[dick_freebird]

The "output offset voltage" will become an input offset
voltage term, by the feedback network.

You have three choices. Tolerate it, trim it or create an
active cancellation scheme (e.g. chopper). If you have
a systematic offset then tolerating it is not likely going
to fly. A random offset is "just" a yield detractor. A big
deterministic offset probably makes the part a loser.
You want to figure out how much of output offset, is
input offset times gain.

 

[sutapanaki]

Since you are simulating a post-layout view under DC conditions and you see an offset, that means most probably you have some systematic asymmetry in your layout. At this point you better find and correct it.

 

[Junus2012]

Dear friends,

thank you for your reply,

it looks like I have systematic offset error in the layout because this problem was not appearing in the schematic,

I am little confused in the way to measure it, first of all I am defining the output offset voltage as the difference between the ideal VOCM and the x value of the intersection value between vo+ and vo-, I am doing this under open loop condition, or do I need to test under closed loop condition with gain = 1.

If I want to tolerate it just for the purpose of simulation without applying active scheme like chopper, what shall I do, for example in single ended op-amp we connect a dc voltage with value of offset voltage at one of the inputs to compensate the offset, but I don't know how to do with the fully differential ampliifer,

my last question, what will be the problem on performance if I live with the offset voltage without killing it, will it affect any other charasetricts

thank you very much

 

[Dominik Przyborowski]

I'm a bit uncertain whether bsim3 models contains any WPE or LOD parameters. It means, that if dc level differs between schematic and extracted netlist, something is wrong with extraction.

 

[Junus2012]

I'm a bit uncertain whether bsim3 models contains any WPE or LOD parameters. It means, that if dc level differs between schematic and extracted netlist, something is wrong with extraction.

Thank you very much for your help

Might be the difference is coming from the layout exctracted parasatic resistors which is becoming non ideally symmetrical, and as long as I am performing the open loop test then it is multiplied by a high gain value, that is was I wanted to confirm from you if it is possible to simulate this offset error using the closed loop gain =1

 

[sutapanaki]

I don't really think so but if you are really in doubt you can easily make a C only extraction with no parasitic resistors and see what you get.
Also, the fact that you suspect uneven parasitic resistors already suggests systematic asymmetries iin the layut because a fully differential structure is is usually laid out symmetrically with every thing the same on both sides.

 

[dick_freebird]

You might look for discrepancies in things like W, M,
W*M in the amplifier netlists. Mirror ratios can be bent
by (say) putting a 10/2*8 reference device to bias
20/2*4 devices, where simple math says 1:1 but any
deltaW will give you a few-% width mismatch while
LVS permute-parallel rules will call them identical.

Schematic should express the layout realities, in the
end. Maybe you have not completed that "truing-up"
and it's the schematic that is being unrealistic (or
at least, not completely realistic).

You would expect a low power amplifier to be fairly
insensitive to interconnect parasitic resistance,
microamps times fractional ohms. But use local
interconnect or poly levels, and then maybe not so
negligible.

You do not mention just how bad the output mismatch
really is.

 

[timof]

Things to check:

1. devices are matched (all instance parameters are the same, for matched devices, for all fingers).

2. Parasitics (parasitic resistance) - should be matched as well.

(Doing it manually / visually is very difficult and time consuming.)

 

[Junus2012]

By the way guies, I have simulated the circuit under closed loop condition with gain = 1, and the result is ginving me equal voltages Vo1 = Vo2 = VCM

 

[dick_freebird]

When you say "equal", just how "equal"?

A "trivial" 10uV input offset turns into a 1mV
output offset at A=100 closed loop.

Peculiar issues like chopper switch charge
injection (don't know specifically, if) can be a
lot more significant in a closed loop config with
high source & FB impedance, than a bare A=1
"wraparound" where input impedances are
Zfb||Zin.

And there can also be output ohmic issues, if
you are selecting a feedback network impedance
that taxes the output drive current appreciably
(then you have a transconductance gain error
voltage imposed on the input, to make it so).