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LDO transient performance enhancement circuit understanding

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For the following LDO circuit, how does the transient performance enhancement circuit sub-block in green color works ?

AvbLGX8.png
 
I tried to replicate the above LDO circuit in LTSpice, but it does not work yet ....

ium7yH0.png


p6Ae47X.png
 

Attachments

  • LDO_ver_1.zip
    4.3 KB · Views: 119

Where is your transient source so you expect a transient response ??
You have to change VDD by transient STEP PULSE source to achieve a transient response..Otherwise everything is in steady state response so DC ..
 
For this LDO circuit , I have pretty good transient output voltage V(vout) for a 100k sine input on Vin.

But it goes very bad when I use 1MEG sine input on Vin.

Any advice ?

oHjwRsu.png


N3J1k8f.png


686xNmI.png


LDO.asc

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TEXT 64 32 Left 2 !.lib mosfet_018.lib
TEXT 344 32 Left 2 !.tran 100u
TEXT 520 32 Left 2 !;.ac dec 100 1 1g
 

Why don't you filter the constant-Gm bias circuit? And you have uA consumption, PSRR is strongly frequency dependent, these 2 things together result above. No surprises.
 
it is consuming less than 300uA , and as I have tried, increasing current limiting resistor R3 value does not really help in improving PSRR.

Do you have a decent CMOS circuit for filtering the constant-Gm bias circuit ?
 

I don't have, I only suggest to add capacitors in paralel with the gate-source of M2 and M10. Or add series resistor with the gates, maybe the combination of them. And don't use minimal length for transistors where it is not necessary, that improves PSRR.
 
And don't use minimal length for transistors where it is not necessary, that improves PSRR.
Click to expand...

How is minimal length related to PSRR ?
 

What do you think about the following gain margin and phase margin plot ?

How to move the zero at the high frequency zone to lower frequency range ?

JXvzK7I.png


BlxvhQL.png


LDO_gain_phase_margin.asc

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SYMBOL voltage -512 256 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName Vin
SYMATTR Value SINE(3.3 1 1MEG)
SYMBOL cap 1936 912 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL res 3456 992 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 3456 1376 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL pmos4 1968 688 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=8
SYMATTR InstName M18
SYMATTR Value PM
SYMBOL cap 1824 640 R0
SYMATTR InstName C2
SYMATTR Value 1p
SYMBOL pmos4 2432 128 M0
WINDOW 123 -77 116 Left 2
SYMATTR Value2 L=0.18u W=6u m=8
SYMATTR InstName M19
SYMATTR Value PM
SYMBOL pmos4 3424 128 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=2000
SYMATTR InstName M20
SYMATTR Value PM
SYMBOL pmos4 2416 656 M270
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=1
SYMATTR InstName M22
SYMATTR Value PM
SYMBOL pmos4 2464 720 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=1
SYMATTR InstName M21
SYMATTR Value PM
SYMBOL pmos4 3104 128 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=8
SYMATTR InstName M23
SYMATTR Value PM
SYMBOL nmos4 3104 1040 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=8
SYMATTR InstName M24
SYMATTR Value NM
SYMBOL nmos4 2832 1040 M0
WINDOW 123 -77 114 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M25
SYMATTR Value NM
SYMBOL nmos4 2560 1040 M0
WINDOW 123 -77 114 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M26
SYMATTR Value NM
SYMBOL pmos4 2736 128 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M27
SYMATTR Value PM
SYMBOL voltage 688 992 M0
SYMATTR InstName Vref
SYMATTR Value DC 1.1V
SYMBOL nmos4 -160 1200 M0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M1
SYMATTR Value NM
SYMBOL nmos4 48 1200 R0
WINDOW 123 -43 119 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M3
SYMATTR Value NM
SYMBOL nmos4 -160 896 M0
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M4
SYMATTR Value NM
SYMBOL nmos4 48 896 R0
WINDOW 123 -43 119 Left 2
SYMATTR Value2 L=0.18u W=6u m=2
SYMATTR InstName M5
SYMATTR Value NM
SYMBOL pmos4 -160 128 M0
WINDOW 123 -77 116 Left 2
SYMATTR Value2 L=0.18u W=6u m=1
SYMATTR InstName M6
SYMATTR Value PM
SYMBOL res -192 1360 M0
SYMATTR InstName R3
SYMATTR Value 22k
SYMBOL voltage 2288 1264 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 60 56 VTop 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMATTR Value2 AC 1
TEXT 64 32 Left 2 !.lib mosfet_018.lib
TEXT 344 32 Left 2 !;.tran 100u
TEXT 520 32 Left 2 !.ac dec 100 1 1g
 

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  • LDO_ver_3.zip
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Last edited:

Why does the transient simulation around 10us have a lot of noise ?

Where is the actual root cause for such deterministic noise at 10us after simulation starts ? And any idea how to eliminate it entirely from the noise source ?

TR8NZo4.png


EjTU402.png
 

At every low supply voltage moment there is some "noise" on the output. I think it tells that your circuit is unstable at lower supply voltages. Simulate stability with different supply voltage values, check gain and phase margin.
I guess your transistors are not good for your application. What kind of model are you using?
 
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    promach

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At lower supply voltage such as 2.5V , LDO does not work anymore.

I am using this mosfet model

What do you suggest ?

I am not sure if FreePDK15 model could actually be used with LTSpice

In this case, I think I need some other mosfet models.
 

how much is the minimum and maximum supply voltage do you want? choose transistors which are fit for both. or choose a simplier LDO. or if it is for learning purpose simply don't use low supply.
 
Could you show an open-loop gain plot? It is stability issue, you have to improve stability. You have to find which transistor enters triode region when you apply low supply. And make surre these transistors can operate on 5V.
 

3HsdZqd.png


erxCSNT.png


Note: output load capacitance, CL = 1uF

and changing Vin parameters such as 3.3V to 2.5V , as well as lowering the Vin frequency from 1MHz to below 1kHz do not change the phase margin.
 
Last edited:

Are you sure above figure is simulated next to 2.5V DC supply? I think we should see some minor changes at least between 2.5V and 3.3V values. Try to plot both on the same figure. Or you could analyse what is the minimum supply which cause significant change in AC behaviour. BTW what do you mean by lowering frequency parameters do not change the phase margin, this is an AC plot?
 

BTW what do you mean by lowering frequency parameters do not change the phase margin, this is an AC plot?
Click to expand...

Look at Vin SINE() parameters
 

I have uploaded the LDO circuit at https://github.com/promach/LDO

I have few questions :

1. Why in the second bode plot (which might be problematic PSRR), gain going up near unity-gain frequency is often a sign of instability ?
2. Why is there some initial noise disturbance around 10us during start-up ?
3. What is the purpose of M2 and M26 ?
4. Could anyone explain the mechanism of transient performance enhancement circuit consisting of M19, M27, M23, M24 and M25 ?
5. Any suggestion on suitable test circuit for load regulation metric check ?

**broken link removed**
 

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