h_upadhyay
Newbie level 3
I have to generate a two different sine wave(1st sine wave normal sine wave which is generate from 0 degree and 2nd one phase shifted sine wave ) using Verilog, and on google, I found something related to it but somehow I didn't understand. So, could anyone explain to me the logic behind this code?
but here what is the logic for ?
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
Code:
module sine_cos(clk, reset, en, sine, cos);
input clk, reset, en;
output [7:0] sine,cos;
reg [7:0] sine_r, cos_r;
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
always@(posedge clk or negedge reset)
begin
if (!reset) begin
sine_r <= 0;
cos_r <= 120;
end else begin
if (en) begin
sine_r <= sine;
cos_r <= cos;
end
end
end
endmodule
but here what is the logic for ?
assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};