Ringing on PSFB secondary switches

[sabu31]

Dear All,

I have designed a PSFB DC-DC converter designed for with input voltage range of 105 to 135 V and output voltage range of 48 V to 90 V with power rated at 750W. The transformer turns ratio is 1:1.5:1.5 (Centre tapped). The resonant inductor value is calculated at 4uH. However when I am testing , even at 30V input and 20 V output heavy ringing is observed at secondary side reaching upto 350V peak. I am attaching the waveforms for your reference. I have put a snubber of 1nf and 50ohms across output switches. What should be done for rectifying this ringing issue.

https://imgur.com/hvR5g4n
https://imgur.com/41pA6Nn

The first image shows Transformer current and Voltage across switches in one leg of primary. The second image shows secondary Transformer current and voltage across switches in secondary. Please let me know what else can be done to avoid ringing.

 

[mtwieg]

Post your full schematic, with component values. 4uH is very small for a resonant inductor. Do you know what the transformer's leakage inductance is?

 

[sabu31]

Thanks Mtweig for the reply,

The transformers leakage inductance is 0.85micro Henry at primary side. Since Primary current is around 10 -15 Amps, based on the output capacitance of MOSFET IRF4768PBF, I am getting calculated value of 4 uH. The magnetizing inductance is 376uH when seen from primary. I have attached schematic.
https://imgur.com/NlDBdrs

 

[mtwieg]

At max load, yes 4uH should be enough to provide ZVS on the FETs. Are you testing at max load?

Are you actually using that capacitor in series with the primary? It might be ringing with your leakage inductance...

 

[FvM]

I wonder if the primary voltage spikes are measurement artefacts (bad probe circuit) or real (bad layout).

 

[sabu31]

Hi mtweig,

The capacitor was used to prevent saturation of Transformer, due to imbalance. It was mentioned in application note. I am not able to test at desired power level and voltage level due to the severe spikes. I am also wondering whether PSFB is better than Full Bridge with SiC Devices. Please suggest how should trouble shooting be approached. The snubber (secondary side) is also getting warm quickly. Is any snubber required at primary side.

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I wonder if the primary voltage spikes are measurement artefacts (bad probe circuit) or real (bad layout).

Hi FvM,

The secondary spikes are sever, come upto 380V when output voltage is only 20 V. The snubber is also getting warm. Is PSFB advantageous over FB when turns ratio is nearly 1. I have seen that most application notes use PSFB for 400V to 12 V step down or 400V to 48 V step down. My application requires (105 to 120V input to 48 to 90V). Are there any other alternative topology for 750W. How about full bridge with SiC switches and synchronous rectification on secondary.

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The second image shows Transformer current and Voltage across switches in one leg of primary. The first image shows secondary Transformer current and voltage across switches in secondary. Please let me know what else can be done to avoid ringing.[/QUOTE]

 

[sabu31]

Hi all,

Any suggestions regarding ringing in PSFB. Does magnetizing inductance play a role in the ringing. Say we if we have a Lm of 300uH as compared to 1mH, what could be the effect.

 

[mtwieg]

Hi mtweig,

The capacitor was used to prevent saturation of Transformer, due to imbalance.

Typically the PSFB is done with current mode control, in which case this capacitor is not needed...

I am also wondering whether PSFB is better than Full Bridge with SiC Devices. Please suggest how should trouble shooting be approached. The snubber (secondary side) is also getting warm quickly. Is any snubber required at primary side.

I wouldn't expect a hard switched full bridge to outperform a PSFB in an equivalent application. Though the hard switched bridge may be easier for you debug.

The secondary spikes are sever, come upto 380V when output voltage is only 20 V.

380V spikes on 20V pulses would indicate some major issue with parasitic inductance and/or improper driving of the FETs. But the waveforms you posted don't show this, at least not on the secondary side. In fact the secondary waveforms (pink and green) suggest that the synchronous rectifiers aren't being controlled properly, and that their body diodes aren't even conducting. Putting a light load on the output might fix that...

 

[FvM]

The secondary spikes are sever, come upto 380V when output voltage is only 20 V.

You didn't yet post secondary waveforms with 380V ringing. Where do you see it? How is it exactly measured?

 

[sabu31]

You didn't yet post secondary waveforms with 380V ringing. Where do you see it? How is it exactly measured?

Hi FVM,

I am attaching secondary waveforms and transformer current in secondary



[found at: i. imgur. com/ hvR5g4n. jpg]

Its measured using a differential voltage probe across switch legs. Also what do you thing of suitability of PSFB vs FB with SiC when Turns ratio of transformer is nearly unity with (input voltage 105 to 120 and output nearly 48 to 90) . In case of PSFB i need to use Np:Ns upto 1:2 due to duty cycle loss.

 

[Easy peasy]

How are you achieving the half turn on the secondaries? if not done right this can introduce significant leakage on the sec side and cause the ringing

Check that the ringing observed is not simply CM effect, put the probe and the gnd lead on the same point and see if you get a flat line of pick up the "ringing"

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what is the reverse recovery of your output fets? if they are not turned off soon enough - you will get these problems ...

 

[sabu31]

How are you achieving the half turn on the secondaries? if not done right this can introduce significant leakage on the sec side and cause the ringing

Check that the ringing observed is not simply CM effect, put the probe and the gnd lead on the same point and see if you get a flat line of pick up the "ringing"

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what is the reverse recovery of your output fets? if they are not turned off soon enough - you will get these problems ...

HI Easy peasy,

I am using primary turns of 7 and secondary turns of 11 and 11 (Centre Tap with each winding 11). Which gives approximately 1:1.5 turns ratio.
The secondary diode reverse recovery is 250ns app (IPW60R031CFD7). The switching frequency is 60Khz. While calculating I am getting core size of ETD59 which is looking high for a 750W converter. Any other alternative converter for this power range as I have less time for trouble shooting.

 

[FvM]

I am attaching secondary waveforms and transformer current in secondary

Turns out that the waveforms in post #1 are flipped (first image secondary, second image primary). Should be mentioned earlier.

Measurement "across switch legs" means Vds? But what's the gate waveform?

 

[Easy peasy]

hi there, assuming dead time on the output fets, their internal diodes will carry current - they will have to reverse recover when the primary power pulse is applied - assuming continuous current in o/p choke - this is the source of the spiking/ringing on the output

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lack of good solid bus de-coupling on the pri side could well be the cause of volt spiking on the pri side - please show picture of layout and sch.

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at light load snubbing will be needed - and it is a good idea to have it anyway for RFI ... esp on o/p diodes/fets

 

[treez]

The secondary diode reverse recovery is 250ns app

Yes i second that from EasyPeasy, 250ns is a long trr for this kind of service.

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The following might be worth reading , and shows an adjustment to the PSFB, so as to mitigate the probelm of ringing on the secondary diodes of the PSFB....



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Here is a relevant thread on sec ringing for PSFB
https://www.edaboard.com/showthread...=phase+shift+full+bridge+massively+over-hyped

....this used to be (maybe still is?), the most highly read thread on edaboard.

 

[sabu31]

Hi all,

Thansk Easy Peasy and treez. I think that could be the cause of ringing along with layout . I have a query whether, the PSFB is a good topology for variable output from 48 V to 90V or is there any other alternative topology.

 

[treez]

Comparing Phase shift full bridge converter with LLC converter.............

Page 7 of the pdf linked here says...
…………………………………………………………………………….
“Design considerations of the power MOSFET in the primary side LLC resonant converter are relatively simple compared to a phase-shifted full-bridge converter, as it is not affected by leading or lagging waveforms with regards to the power MOSFET.”
…………………………………………………………………………….

The document is called “Primary Side MOSFET Selection for LLC Topology”....
https://www.infineon.com/dgdl/Infin...y.pdf?fileId=5546d46147a9c2e40147d3430e927e5d

.....................
LLC is probably worse than PSFB for your range of vin and vout....since you are only at 750W, i believe a straight full bridge with sync rects is the way to go for you.
....................................................................

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The PSFB has some pretty nasty failure modes if not mitigated.....the attached folder has docs on this..

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By the way, if you wish, here is a link to my free SMPS course.
This is the link from my google drive
(It has a folder on PSFB, which i cant attache here as its too big)

https://drive.google.com/open?id=1cmk81KxXA7-EliHHWr8ZimpEp7HCMIcY

Please tell me if it doesnt work.

 

[sabu31]

Comparing Phase shift full bridge converter with LLC converter.............

Page 7 of the pdf linked here says...
…………………………………………………………………………….
“Design considerations of the power MOSFET in the primary side LLC resonant converter are relatively simple compared to a phase-shifted full-bridge converter, as it is not affected by leading or lagging waveforms with regards to the power MOSFET.”
…………………………………………………………………………….

The document is called “Primary Side MOSFET Selection for LLC Topology”....
https://www.infineon.com/dgdl/Infin...y.pdf?fileId=5546d46147a9c2e40147d3430e927e5d

.....................
LLC is probably worse than PSFB for your range of vin and vout....since you are only at 750W, i believe a straight full bridge with sync rects is the way to go for you.
....................................................................

- - - Updated - - -

The PSFB has some pretty nasty failure modes if not mitigated.....the attached folder has docs on this..

- - - Updated - - -

By the way, if you wish, here is a link to my free SMPS course.
This is the link from my google drive
(It has a folder on PSFB, which i cant attache here as its too big)

https://drive.google.com/open?id=1cmk81KxXA7-EliHHWr8ZimpEp7HCMIcY

Please tell me if it doesnt work.

Hi Treez,

Thank you for the suggestion.

 

[Easy peasy]

There is no doubt that phase shift full bridge can be made to work - the slow o/p diodes in this specific case mean that a lot of o/p snubbing is required. Changing dead time timing with load for the passive ( lagging) leg is important, see UCC3879 data sheet and app notes, for some apps it is usual to have a separate choke in series with the Tx and diodes from the other side of this choke to rail, relatively low leakage in the main Tx is helpful.