[SOLVED] Techniques for logic cell estimation - FPGA

[mjuneja]

Can somebody share what are the best techniques in FPGA design that can be used to estimate the logic cell utilisation in an FPGA even before the RTL is written in (VHDL or verilog) so that FPGA selection can be done accordingly to avoid last minute surprises.

Thanks

 

[TrickyDicky]

First of all - decide what interfaces you need.
Do you need a 10G Phy? or just 1G? How many do you need? Do you need a PCIE hard core? Hardcore CPU? This will narrow the field down somewhat
Next - what peripherals? DDR? connectors? some LEDs?
Costs? do you have a cost/ROI performance you're looking to acheive?

Next- Do you have previous experience with a specific vendor? Do you have any existing libraries you might want to use. Do they work on all vendors, or are they tied in to a specific vendor? what toolchains are you going to use.

Only once all of the above are answered, can you move onto RAM estimation and DSP. This is usually fairly straighforward, as you should have some idea of what buffering is needed in your design and volumes can be calculated on interface bandwidths, depth of buffers etc.

And finally logic - IMO its pretty pointless/hard/impossible to do logic estimation without any code. All of the above are usually your limiting factors, and these usually run out before logic. If you have narrowed the above down you'll probably only have a handful of devices to chose from. And here you'll have to factor in feature creap/logic expansion in future. This is normally more easily dealt with by using the smaller of two pin compatible parts and taking the larger one later.

So as you can see, logic estimation is pretty pointless without knowledge of all of the other things.