VHDL "library" and "use.all" clause

[shaiko]

Hello,

Consider the following code before the entity section of a .vhd file:

library x;
use x.all ;

As far as I understand the first line tells the compiler that 'x' is a library and the second line makes all the packages in this library visible for the entity to follow.
Am I correct?

 

[TrickyDicky]

Yes it does, plus all the entities, but it does not make their contents visible.

 

[shaiko]

Re: VHDL "library" and "use.all" clause

but it does not make their contents visible

Mind reading my next question...

If it doesn't make the contents visible, what's the motivation of simply making the package & entity names visible?

 

[TrickyDicky]

Because you don't need the library name when you use direct instantiation for an entity or create a new package from a generic package.

Eg

Inst : entity some_entity
Port map (

That's about the only use I know.

 

[shaiko]

And how would the same instantiation look if I wouldn't use
library x;
use x.all ;
?

 

[niciki]

Then you would use:

Inst : entity [COLOR="#FF0000"]x.[/COLOR]some_entity
Port map (

 

[shaiko]

Consider the following real life scenario:

altera_mf is a library name.
altera_mf_components is a package inside this library.
dcfifo_mixed_widths is a component inside this package.

I tried all of the lines below - and they all compile,
Can you please explain what does each of the lines mean and how they differ between themselves?

inst : entity altera_mf.altera_mf_components.dcfifo_mixed_widths

inst : entity altera_mf_components.dcfifo_mixed_widths

inst : entity altera_mf.dcfifo_mixed_widths

 

[TrickyDicky]

Not really any different.
1. Full path to component.
2. Component from visible package
3. Entity from library

For 1 and 2, your just instantiating the component and mapping it during elaboration
3 is a direct entity instantiation

 

[shaiko]

Is there a way to make visible all packages of a library and all their components with a short code?

Something like:
Library some_library.all.all ;

 

[vGoodtimes]

see https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_merged/#context

-- vhdl 2008
library ieee;
context ieee.ieee_std_context;

-- replaces
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

standard caveats about vhdl-2008 support apply. same for "work" being a special library.

-- this code would be in a file compiled into <some library>.  it doesn't need to be ieee or unisim.
-- it would be accessed with:
-- library <whatever>;
-- context <whatever>.xilinx_with_mostly_safe_math;
context xilinx_with_mostly_safe_math is
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use ieee.numeric_signed."-"; -- gets both one and two arg forms
  use ieee.numeric_unsigned."+";
  use ieee.numeric_unsigned.to_integer;
  library unisim;
  use unisim.vcomponents.all;
end context;

 

[shaiko]

Using
inst : entity altera_mf_components.dcfifo_mixed_widths
and
inst : component altera_mf_components.dcfifo_mixed_widths
Both compile...Is it the same??

 

[TrickyDicky]

Iirc, using component keyword is for a component instantiation, and is optional. Using entity will compile against an entity. If you're compiling in quartus it's a bit more relaxed about things.

Wondering why it's important. Is this just academic?

 

[shaiko]

Wondering why it's important.

Just to know the rules...
I simply noticed that the same code that compiles with Modelsim, generates errors in VCS.