Dynamic IR drop analysis

[ajayg0880]

what are the techniques to reduce dynamic IR drop?

 

[ThisIsNotSam]

better power distribution, more coupling.

 

[kumar_eee]

Better PG routing, Adding de-cap cells, spread the cells if you're in early stage.

 

[gstekboy]

Good PG grid will solve almost all the IR problems.

 

[wimarshal]

Per my experience, there are several items can be considered for high dynamic IR drop region:

1. To use lower driving strength cells, such as to replace X10 to X8, etc.
2. To have the cells spread instead of placed locally.
3. Have more PG grid
4. Add more decap cells as possible.
5. Consider whether the power disspition is reasonable.

Hope this helps.

 

[kumar_eee]

Per my experience, there are several items can be considered for high dynamic IR drop region:

1. To use lower driving strength cells, such as to replace X10 to X8, etc.
2. To have the cells spread instead of placed locally.
3. Have more PG grid
4. Add more decap cells as possible.
5. Consider whether the power disspition is reasonable.

Hope this helps.

Perfect Answer.

 

[arvinraj]

Per my experience, there are several items can be considered for high dynamic IR drop region:

1. To use lower driving strength cells, such as to replace X10 to X8, etc.
2. To have the cells spread instead of placed locally.
3. Have more PG grid
4. Add more decap cells as possible.
5. Consider whether the power disspition is reasonable.

Hope this helps.

Best answer.
One more thing to add: The cell that sinks the most causing large IR drop is usually having a large load cap. Consider lowering load along with the drive strength.

 

[dick_freebird]

If your concern includes I/Os, use of slew rate limited and
current-limited (e.g. LVDS) types will help ground bounce
(a fellow traveler of core I*R drops, as VSS is often common
(while V_core and V_io are often not).

Clock trees that put a big driver against a heavily loaded
net are good for clock uniformity but bad for V_core
spiking. A tapered tree where final stages are closer to
point of use, and scaled to the driven load, is likely better.

A little bit of skew can broaden the consequential current
spike from all of the driven 'flops but reduce its height in
proportion.

 

[Tieny]

As DFT role, better pattern distribution for HATPG and MBIST controllers .