Verilog testbench help!! (bit urgent)

[sonika111]

Hi all

I am trying to convert a big VHDL process block in a testbench into Verilog equivalent . It is not sensitive to anything but the statements occur in a sequence. There are some fileio operations and depending on the field the signals are assigned.....

I am struggling to decide if I can incorporate all this in inital block or I need to use always block. Also how to use the differnt fields of the line and direct the assignments accordingly(say each line that is read from .txt file has 4 fields, hex,hex.hex,string)

I would appreciate if any one can help me solve this problem??(by giving some code snippet please?) Many thanks

- - - Updated - - -

Another qusetion please if I decide to use initail block and I need to wait for example for posedge of clk or posedge of any_signal

is this valid

initial begin @posedge(clk);// or any signal...

Please advise(if it is not correct)what I need to do??

I think I would not prefer a always block as everything does not wait for posedge clk;
what is theway to deal with this?

- - - Updated - - -

Also please function in verilog to convert hex value into integer

- - - Updated - - -

This is equivalent to (count /= to_integer(unsigned(hex_value)))

- - - Updated - - -

(count /= to_integer(unsigned(hex_value)))

 

[ads-ee]

Why are you converting a VHDL testbench to Verilog? It is normal to have mixed mode simulations, which is why simulators support both languages and aren't requiring you to buy separate licenses for each language.

If you want to run in sequence use an initial block with the @(posedge clk) to generate signals synchronous to the clock. You can also use tasks to package up sequences that you need to repeatedly use in different places and call these in the initial block.

When it comes to testbenches, think of the code as software instead of synthesizable hardware.

 

[sonika111]

Thanks very much. I have VHDL design and would ultmately want a system verilog testbench with all fancy classes which I am new to and need some practise/help

I would also request you if you can answer other bits such as
function in verilog to convert hex value into integer

(count /= to_integer(unsigned(hex_value))) ... convt this to verilog.....

Thanks very much

- - - Updated - - -

Request: Please don't close it until it is answered completely

- - - Updated - - -

Also please help me witth this as well
Also how to deal with textio with more fields... What is equivalent of HREAD of VHDL(when you have to read first field in hex in verilog ... do we use $fgets
what do we do after $fgets(line,fd) to get first field.
BTW what does $fscanf(file,"%h",data); do will it store the first field into bus data. Thanks very much

- - - Updated - - -

if not then how to achieve that please

 

[TrickyDicky]

VHDL can do alot of what SV can do with VHDL 2008. Dont be getting over excited about SV. Yes, while "fancy classes" are good, and powerful, they also bring complexity and training is likely to be required. VHDL can do so much and people just jump straight into SV and UVM without really understanding what they really need. You need a good testbench. A SV testbench is not automatically "good" just because it is SV (although many engineers and managers have fallen into this trap). Badly written SV is still just Badly written.

So, you are converting your perfectly good VHDL to Verilog just because you've been alured by "fancy classes"? have you even tried expanding your VHDL knowledge, so you dont need to re-write what you've already written?

 

[sonika111]

Thanks;quite true.

I am still looking for couple of a answers if you all can provide; I would really appreciate that.

 

[TrickyDicky]

(count /= to_integer(unsigned(hex_value)))

Equivolent in verilog:

count != hex_value

Remember, verilog is much less strict on types, and integer 4 state types can just be compared as if they are all integers. But remember to look out for the differences between ==, ===, !=, !==. Verilog and SV are more dangerous places to be - get used to using the line debugger in your simulator.

For file reading, yes you're pretty correct, have you tried google for these things? ASIC-world is a pretty good Verilog/SV reference

https://www.asic-world.com/scripting/file_io_c.html

 

[sonika111]

Thanks do you think that following extract will store the first hex data of the file fd into data which I can later use to branch on the basis of the value...
$fgets(line,fd);
$fscanf(file,"%h",data);
if(data == ) begin

etc etc

I really need to get this right? Thanks very much

- - - Updated - - -

Sorry it should be $fscanf(line,"%h",data);..

 

[TrickyDicky]

$fscanf scans from a file
$sscanf scans from a string

You need:

---

Code Verilog - [expand]
1
2
3
$fgets(line,fd);
$sscanf(line,"%h",data);
if(data == ) begin

---

Using google/verilog reference, compiling the code and running the code should tell you if you made simple mistakes like this (and probably quicker than posting small code questions on this forum).

 

[sonika111]

Thanks very much.

1 more quick help please. I would really appreciate that

Instead of VHDL construct used in VHDL testbench
if( fcmd=0)
else if(fcmd=1)
else if(faddr=0) ; what would you advise me in verilog (its counterpart please). If you could please advise me urgently

I feel stuck without this

Many thanks

 

[TrickyDicky]

use == instead of =
I also suggest purchasing a verilog reference guide book (or find one on the internet!)

 

[sonika111]

Thanks. That I know.. The problem is that it appears there is not else if in verilog

 

[TrickyDicky]

verilog has else if, but not elsif

 

[sonika111]

Thanks very much. The problem is that I get an extra compilation error when I use else; Are you sure it exists as the Verilog reference manual suggests that... I was thinking of using if(cond) begin end... for all my conditions separately....


Please advice

 

[TrickyDicky]

You need to post the code that wont compile and the error. Not just a snippet that is otherwise fine.

 

[sonika111]

Thanks very much for your quick responses. I really appreciate that:

I am using it in initial block of testbench, can that be a problem. Thanks very much

 

[vGoodtimes]

I suspect this is Verilog's C-style if statements which accept exactly one statement when not used with begin/end. I advise using begin/end every time unless there is a good reason to skip them. I also advise placing them on the same line, eg "end else if (x) begin". even though it looks odd to have "end" at the start of a line, it lines up nicely with VHDL's if/else style.

 

[sonika111]

thanks very much everyone . I can now compile but while simulating I get the following error Illegal inout port connection for port 'pp'. It is a inoot port and I have defined it as logic [3:0] pp in my .sv file (which uses mostly verilog at the moment and have made assignments as
0}};
pp <= {$bits(pp){1'bZ}}; Can you guys please advise me why? and how to get rid of this error.

Also I am getting some warnings as ''Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns)"" ??

Thanks.. This error is not helping me move forward. Many thanks

 

[ThisIsNotSam]

thanks very much everyone . I can now compile but while simulating I get the following error Illegal inout port connection for port 'pp'. It is a inoot port and I have defined it as logic [3:0] pp in my .sv file (which uses mostly verilog at the moment and have made assignments as
0}};
pp <= {$bits(pp){1'bZ}}; Can you guys please advise me why? and how to get rid of this error.

Also I am getting some warnings as ''Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns)"" ??

Thanks.. This error is not helping me move forward. Many thanks

google is your friend. you questions are very basic and have been asked 100s of times.

 

[sonika111]

Thanks. I tried. Could not find anything similar to mine. Please reply

I am not using it in the assign statement: I am using blocking assignment in an in intial block...
I see some suggestions as
assign bidir_pin = out_oe ? out_sig : 1'bz; It might not work for me

 

[sonika111]

I will try to explain better so that you guys can help me

This exists in my design and io_data_bus declared as inout

assign io_data_bus = (output_enable) ? data_out : {(16){1'bz}};

In my testbench I have something like at few places

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
initial
begin
...
.... 
io_data_bus  <= {$bits(io_data_bus ){1'bZ}}
end
 
initial
begin
...
.... 
io_data_bus  <= data
end

---

the output_enable is not on the port list of my module.....

What should I do in the testbench(please if you could provide the corrected snippet of testbench ); so that I don't get this error...Many thanks

- - - Updated - - -

I came across this post Is this my solution

https://www.edaboard.com/showthread.php?t=42207

I have couple of inouts?? Do I treat them as in this post and I would get correct stimulus??

I am wondering why inout was not a problem in my VHDL testbench?( I didn't have to treat it like this??) and I didn't get such errors